User guide

10–36 Chapter 10: Transceiver Reconfiguration Controller
Understanding Logical Channel Numbering
Altera Transceiver PHY IP Core March 2012 Altera Corporation
User Guide
1 Because all of the channels in a transceiver bank share a PLL, this original numbering
allows the Fitter to select the optimal CMU PLL from a placement perspective by
considering all of the TX PLLs in the bank.
Table 10–27 shows the channel numbers for post-Fitter and hardware simulations. At
this point, you should have assigned channels to pins of the Stratix V device.
Two PHY IP Core Instances Each with Non-Bonded Channels
Non-bonded channels do not share TX PLLs.. For each transceiver PHY IP core
instance, the Quartus II software assigns the data channels sequentially beginning at
logical address 0 and assigns the TX PLLs the subsequent logical addresses.
Table 10–28 illustrates the logical channel numbering for two transceiver PHY IP
cores, one with 4 channels and one with 2 channels.
Table 10–27. Post-Fit Logical Channel Numbers for Eight Bonded Channels
Channel Logical Channel Number
Channel 0 0
Channel 1 1
Channel 2 2
Channel 3 3
CMU (0–4) 8-12
Channel 4 4
Channel 5 5
CMU (5–7) 13–15
Channel 6 6
Channel 7 7
Table 10–28. Initial Number of Eight Bonded Channels
Instance Channel Logical Channel Number
Instance 0
Channel 0 0
Channel 1 1
Channel 2 2
Channel 3 3
CMU 0 4
CMU 1 5
CMU 2 6
CMU 3 7
Instance 1
Channel 0 8
Channel 1 9
CMU 0 10
CMU 1 11