User guide

3–2 Chapter 3: 10GBASE-R PHY IP Core
Release Information
Altera Transceiver PHY IP Core March 2012 Altera Corporation
User Guide
To make most effective use of this soft PCS and PMA configuration for Stratix IV GT
devices, you can group up to four channels in a single quad and control their
functionality using one Avalon-MM PHY management bridge, transceiver
reconfiguration module, and low latency controller. As Figure 3–2 illustrates, the
Avalon-MM bridge Avalon-MM master port connects to the Avalon-MM slave port of
the transceiver reconfiguration and low latency controller modules so that you can
update analog settings using the standard Avalon-MM interface.
This configuration does not require that all four channels in a quad run the
10GBASE-R protocol.
Release Information
Table 3–1 provides information about this release of the 10GBASE-R PHY IP core.
Figure 3–2. Complete 10GBASE-R PHY Design in Stratix IV GT Device
To MAC
To Embedded
Controller
Avalon-MM
connections
10GBase-R PHY
SDR XGMII
72 bits @ 156.25 Mbps
To MAC
SDR XGMII
72 bits @ 156.25 Mbps
Avalon-MM
PHY
Management
Bridge
M
S
S
Low Latency
Controller
S
Transceiver
Reconfig
Controller
Alt_PMA
10GBASE-R
10.3 Gbps
10.3125 Gbps serial
To HSSI Pins
PCS
10GBASE-R
(64b/66b)
S
S
Alt_PMA
10GBASE-R
10.3 Gbps
10.3125 Gbps serial
To HSSI Pins
PCS
10GBASE-R
(64b/66b)
S
S
Table 3–1. 10GBASE-R Release Information (Part 1 of 2)
Item Description
Version 11.1
Release Date November 2011
Ordering Codes
(1)
IP-10GBASERPCS (primary)
IPR-10GBASERPCS (renewal)
Product ID 00D7