User guide

March 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
3. 10GBASE-R PHY IP Core
The Altera 10GBASE-R PHY IP core implements the functionality described in IEEE
802.3 Clause 49. It delivers serialized data to an optical module that drives optical fiber
at a line rate of 10.3125 Gbps. In a multi-channel implementation of 10GBASE-R, each
channel of the 10GBASE-R PHY IP core operates independently. Figure 3–1 shows the
10GBASE-R PHY IP core available for Stratix V devices. Both the PCS and PMA of the
10GBASE-R PHY are implemented as hard IP blocks in Stratix V devices, saving
FPGA resources.
f For a 10-Gbps Ethernet solution that includes both the Ethernet MAC and the
10GBASE-R PHY, refer to the 10-Gbps Ethernet MAC MegaCore Function User Guide.
f For more detailed information about the 10GBASE-R transceiver channel datapath,
clocking, and channel placement, refer to the “10GBASE-R” section in the Transceiver
Protocol Configurations in Stratix V Devices chapter of the Stratix V Device Handbook.
Figure 3–2 illustrates a multiple 10 GbE channel IP core in a Stratix IV GT device. To
achieve higher bandwidths, you can instantiate multiple channels. The PCS is
available in soft logic for Stratix IV GT devices; it connects to a separately instantiated
hard PMA. The PCS connects to an Ethernet MAC via single data rate (SDR) XGMII
running at 156.25 megabits per second (Mbps) and transmits data to a 10 Gbps
transceiver PMA running at 10.3125 gigabits per second (Gbps) in a Stratix IV GT
device.
Figure 3–1. 10GBASE-R PHY with Hard PCS with PMA in Stratix V Devices
10GBASE-R PHY IP Core
10/3125 Gbps serial
XFI/SFI
Network
Interface
Stratix V FPGA
PMA
PMD
Copper
or
Optical
Hard PCS
10GBASE-R
64b/66b
Scrambler
PRBS
Gearbox
SDR XGMII
72 bits @ 156.25 Mbps
Avalon-MM
Control & Status