User guide

Chapter 10: Transceiver Reconfiguration Controller 10–21
Channel and PLL Reconfiguration
March 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
Table 10–20 lists the PLL reconfiguration registers.
1 All undefined register bits are reserved and must be set to 0.
.
Channel and PLL Reconfiguration
You can use channel and PLL reconfiguration to dynamically reconfigure the channel
and PLL settings in a transceiver PHY IP core. Among the settings that you can
change dynamically are the data rate and interface width.
The Transceiver Reconfiguration Controller’s Streamer Module implements channel
and PLL reconfiguration. Refer to the “Streamer Module” on page 10–22 for more
information about this module.
1 Channel and PLL reconfiguration are available for the Custom and Low Latency PHY
IP cores.
Channel Reconfiguration
If you turn on Enable channel/PLL reconfiguration in the Transceiver
Reconfiguration Controller GUI, you can change the following channel settings:
■ TX PMA settings
■ RX PMA settings
■ RX CDR input clock
Table 10–20. PLL Reconfiguration Offsets and Values
Offset Bits R/W Name Description
0x0 [2:0] RW
logical refclk selection
When written initiates reference clock change
to the logical reference clock indexed by bits
[2:0].
For the Custom and Low Latency PHY IP
cores, this index refers to the Number of input
clocks on the Reconfiguration tab. You can
specify up to 5 input clocks.
0x1 [2:0] RW
logical PLL selection
When written initiates a clock generation block
(CGB) switch to logical PLL indexed by bits
[2:0].
For the Custom and Low Latency PHY IP
cores, this index refers to the Number of TX
PLLs selected on the Reconfiguration tab. You
can specify up to 4 input clocks. If you set the
Main TX PLL logical index to 0, the Quartus II
software initializes your design using the first
PLL defined.
0x2 [24:0] RO
refclk physical mapping
Specifies the logical to physical refclk for
current logical channel.
0x3 [14:0] RO
PLL physical mapping
Specifies the logical to physical clock
generation block word for current logical
channel.