User guide

10–20 Chapter 10: Transceiver Reconfiguration Controller
PLL Reconfiguration
Altera Transceiver PHY IP Core March 2012 Altera Corporation
User Guide
Table 10–19 lists the PLL reconfiguration registers that you can access using
Avalon-MM read and write commands on reconfiguration management interface.
1 All undefined register bits are reserved.
Table 10–19. PLL Reconfiguration Registers
Addr Bits R/W Register Name Description
7’h40 [9:0] RW
logical channel number
The logical channel number. Must be specified when
performing dynamic updates. The Transceiver
Reconfiguration Controller maps the logical address to the
physical address.
7’h41 [9:0] R
physical channel address
The physical channel address. The Transceiver
Reconfiguration Controller maps the logical address to the
physical address.
7’h42
[9] R
control and status
When asserted, indicates an error. This bit is asserted if any
of the following conditions occur:
■ The channel address is invalid.
■ The PHY address is invalid.
■ The address offset is invalid.
[8] R
MIF Busy . When asserted, indicates that a reconfiguration
operation is in progress.
[1] W
Read . Writing a 1 to this bit specifies a read operation.
[0] W
Write . Writing a 1 to this bit specifies a write operation.
7’h43 [3:0] RW
pll offset
Specifies the 4-bit register address used for indirect to the
PLL registers on the reconfiguration bus. Refer to
Table 10–20 for offsets and values.
7’h44 [15:0] RW
data Specifies the read or write data.