User guide

Chapter 10: Transceiver Reconfiguration Controller 10–15
DFE
March 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
Table 10–14 describes the DFE registers that you can access to change DFE settings.
1 All undefined register bits are reserved and must be set to 0.
7’h1A
[9] R
control and status
Error
. When asserted, indicates an invalid channel or
address.
[8] R
Busy . When asserted, indicates that a reconfiguration
operation is in progress.
[1] W
Read . Writing a 1 to this bit triggers a read operation.
[0] W
Write . Writing a 1 to this bit triggers a write operation.
7’h1B [5:0] RW
dfe_offset Specifies the 6-bit offset of the DFE register.
7’h1C [15:0] RW
data Reconfiguration data for the transceiver PHY registers.
Table 10–13. DFE Registers (Part 2 of 2)
Recon
-fig
Addr
Bits R/W Register Name Description
Table 10–14. DFE Offset and Values (Part 1 of 2)
Offset Bits R/W Register Name Description
0x0
[1] RW
power on
A 0 to 1 transition on this bit triggers DFE calibration.
[0] RW
adaptation engine
enable
Writing a 1 triggers the adaptive equalization engine.
0x1 [3:0] RW
tap 1
Specifies the coefficient for the first post tap. The valid
range is 0–15.
0x2
[3] RW
tap 2 polarity
Specifies the polarity of the second post tap as follows:
■ 0: negative polarity
■ 1: positive polarity
[2:0] RW
tap 2
Specifies the coefficient for the second post tap. The valid
range is 0–7.
0x3
[3] RW
tap 3 polarity
Specifies the polarity of the third post tap as follows:
■ 0: negative polarity
■ 1: positive polarity
[2:0] RW
tap 3
Specifies the coefficient for the third post tap. The valid
range is 0–7.
[3] RW
tap 4 polarity
Specifies the polarity of the fourth post tap as follows:
■ 0: negative polarity
■ 1: positive polarity
0x4 [2:0] RW
tap 4 Specifies the coefficient for the fourth post tap.