User guide

Chapter 10: Transceiver Reconfiguration Controller 10–5
Performance and Resource Utilization
March 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
Performance and Resource Utilization
Table 10–3 shows the approximate device resource utilization for a the Transceiver
Reconfiguration Controller. The numbers of combinational ALUTs and logic registers
are rounded to the nearest 50. Table 10–3 also shows the time required for calibration
and AEQ functions.
Parameter Settings
The Transceiver Reconfiguration Controller is available in the MegaWizard Plug-In
Manager and Qsys design flows. To configure the Transceiver Reconfiguration
Controller IP core in the MegaWizard design flow, click Installed Plug-Ins >
Interfaces > Transceiver PHY > Transceiver Reconfiguration Controller v11.1. To
configure the Transceiver Reconfiguration Controller in Qsys, in the Component
Library, type
Transc in the Search Box. Qsys filters all available components for this
text string and displays the Transceiver Reconfiguration Controller which is in the
Interface Protocols >Transceiver PHY category.
Table 10–3. Resource Utilization
Component ALUTs Registers
Memory
Blocks
M20Ks Run Time
Transceiver Calibration Functions
Offset Cancellation 500 400 0 0 100
μs/channel
Duty cycle calibration 350 400 0 0 70
μs/channel
ATX PLL calibration 650 450 0 4 60 μs/channel
Analog Features
EyeQ 300 200 0 0 —
AEQ 700 500 0 0 40
μs/channel
Reconfiguration Features
Channel and PLL reconfiguration 400 500 0 0 —
(1)
PLL reconfiguration (only) 250 350 0 0 —
(1)
Note to Table 10–3:
(1) The time to complete these functions depends upon the complexity of the reconfiguration operation.