User guide

10–2 Chapter 10: Transceiver Reconfiguration Controller
Altera Transceiver PHY IP Core March 2012 Altera Corporation
User Guide
This user guide describes the features of the Transceiver Reconfiguration Controller. It
also includes descriptions of the accessible transceiver registers, information about the
MIF file format, and examples demonstrating the update procedures. It includes the
following sections:
■ “System Overview” on page 10–3
■ “Device Family Support” on page 10–4
■ “Performance and Resource Utilization” on page 10–5
■ “Parameter Settings” on page 10–5
■ “Interfaces” on page 10–7
■ “Reconfiguration Controller Memory Map” on page 10–9
■ “PMA Analog Controls” on page 10–11
■ “EyeQ” on page 10–12
■ “DFE” on page 10–14
■ “AEQ” on page 10–16
■ “ATX PLL Calibration” on page 10–17
■ “PLL Reconfiguration” on page 10–18
■ “Channel and PLL Reconfiguration” on page 10–21
■ “Streamer Module” on page 10–22
■ “Procedures for Reconfiguration” on page 10–27
■ “Understanding Logical Channel Numbering” on page 10–31
■ “Reconfiguration Controller to PHY IP Connectivity” on page 10–37
■ “Merging TX PLLs In Multiple Transceiver PHY Instances” on page 10–38
■ “Loopback Modes” on page 10–39