User guide

March 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
10. Transceiver Reconfiguration
Controller
The Altera Transceiver Reconfiguration Controller dynamically reconfigures the
analog, channel, and TX PLL settings in Stratix V GX devices. Because the Stratix V
FPGA is a 28-nm device, circuit performance is affected by variations due to process,
voltage, and temperature (PVT). Stratix V devices that include transceivers must use
the Transceiver Reconfiguration Controller to compensate for these variations. You
can also use the Transceiver Reconfiguration Controller to compensate for signal
integrity issues on the PCB or to change channel and TX PLL settings. For example,
you can reconfigure a channel to support Ethernet running at 1 Gbps or 10 Gbps. You
can also change the width of the datapath. The Transceiver Reconfiguration
Controller provides access to the following settings:
■ Transceiver calibration functions
■ ATX PLL calibration
■ PMA analog controls
■ Adaptive equalization (AEQ)
The Transceiver Reconfiguration Controller also provides access to the following
channel and TX PLL settings:
■ The reference clock input to the TX PLL
■ The clock dividers used by the TX PLL
■ The PCS datapath settings
■ Loopback modes: both pre-CDR (clock data recovery) reverse serial loopback and
post-CDR reverse serial loopback are supported
1 In the Quartus II 11.1 release, the Transceiver Reconfiguration Controller is available
for Arria V devices. However, it is not functional. It is available so that you can
include it in your design to establish the connections necessary between the two IP
cores.