User guide

9–22 Chapter 9: Deterministic Latency PHY IP Core
Interfaces
Altera Transceiver PHY IP Core March 2012 Altera Corporation
User Guide
Dynamic Reconfiguration
As silicon progresses towards smaller process nodes, circuit performance is affected
more by variations due to process, voltage, and temperature (PVT). These process
variations result in analog voltages that can be offset from required ranges. The
calibration performed by the dynamic reconfiguration interface compensates for
variations due to PVT.
Each channel and each TX PLL has a separate dynamic reconfiguration interfaces. The
parameter editor provides informational messages on the connectivity of these
interfaces. Example 9–1 shows the messages for a single duplex channel.
0x082
[31:1] R
pcs8g_tx_status Reserved.
[0] RW Reserved —
0x083
[31:6] RW
pcs8g_tx_control Reserved.
[5:1] RW
tx_bitslipboundary_select
Sets the number of bits that the TX bit slipper needs to slip.
To block: Word aligner.
[0] RW
tx_invpolarity
When set, the TX interface inverts the polarity of the TX
data.
To block: 8B/10B encoder.
0x084
[31:1] RW Reserved. —
[0] RW
rx_invpolarity
When set, the RX channels inverts the polarity of the
received data.
To block: 8B/10B decoder.
0x085
[31:4] RW
pcs8g_rx_wa_control Reserved.
[3] RW
rx_bitslip
Every time this register transitions from 0 to 1, the RX data
slips a single bit.
To block: Word aligner.
[2] RW
rx_bytereversal_enable
When set, enables byte reversal on the RX interface.
To block: Byte deserializer.
[1] RW
rx_bitreversal_enable
When set, enables bit reversal on the RX interface.
To block: Word aligner.
[0] RW
rx_enapatternalign
When set in manual word alignment mode, the word
alignment logic begins operation when this bit is set.
To block: Word aligner.
Table 9–18. Deterministic Latency PHY IP Core Registers (Part 3 of 3)
Word
Addr
Bits R/W Register Name Description