User guide

Chapter 9: Deterministic Latency PHY IP Core 9–17
Interfaces
March 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
Transceiver Serial Data Interface
Table 9–14 describes the differential serial data interface and the status signals for the
transceiver serial data interface.
TX and RX Status Signals
Table 9–15 describes the optional status signals for the RX interface.
Table 9–14. Serial Interface and Status Signals
(1)
Signal Name Direction Signal Name
rx_serial_data[<n>-1:0] Input Receiver differential serial input data.
tx_serial_data[<n>-1:0] Output Transmitter differential serial output data.
Note to Table 9–14:
(1) <n> is the number of lanes.
Table 9–15. Serial Interface and Status Signals (Part 1 of 2)
(1)
Signal Name Direction Signal Name
tx_ready Output
When asserted, indicates that the TX interface has exited
the reset state and is ready to transmit.
rx_ready Output
When asserted, indicates that the RX interface has exited
the reset state and is ready to receive.
pll_locked[<p>-1:0] Output
When asserted, indicates that the PLL is locked to the input
reference clock.
rx_bitslipboundaryselectout
[(<n>5)-1:0]
Output
Specifies the number of bits slipped to achieve word
alignment. In 3G (10-bit) mode, the output is the number of
bits slipped. If no bits were slipped, the output is 0. In 6G
(20-bit) mode, the output is (19
− the number of bits
slipped). If no bits were slipped, the output is 19. The
default value of
rx_bitslipboundaryselectout[4:0]
before alignment is achieved is 5'b01111 in 3G mode and
5'b11111 in 6G mode.
Optional Status Signals
tx_bitslipboundaryselect
[(<n>5)-1:0]
Input
This signal is used for bit slip word alignment mode. It
selects the number of bits that the TX block must slip to
achieve a deterministic latency.
rx_disperr[(<n>(<d>/<s>)-1:0] Output
When asserted, indicates that the received 10-bit code or
data group has a disparity error.
rx_errdetect[(<n>(<d>/<s>)-1:0] Output
When asserted, indicates that a received 10-bit code group
has an 8B/10B code violation or disparity error.
rx_syncstatus[(<n>(<d>/<s>)-1:0] Output
Indicates presence or absence of synchronization on the
RX interface. Asserted when word aligner identifies the
word alignment pattern or synchronization code groups in
the received data stream. This signal is optional.
rx_is_lockedtoref[(<n>(<d>/<s>)-1:0] Output
Asserted when the receiver CDR is locked to the input
reference clock. This signal is asynchronous. This signal is
optional.