User guide

Chapter 9: Deterministic Latency PHY IP Core 9–15
Interfaces
March 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
■ <p>—The number of PLLs
1 The block diagram shown in the parameter editor labels the external pins with the
interface type and places the interface name inside the box. The interface type and name
are used in the _hw.tcl file that describes the component. If you turn on Show signals,
the block diagram displays all top-level signal names.
f For more information about _hw.tcl files refer to refer to the Component Interface Tcl
Reference chapter in volume 1 of the Quartus II Handbook.
The following sections describe the signals in each interface.
Figure 9–3. Deterministic Latency PHY Top-Level Signals
tx_parallel_data[<n><w>-1>:0]
tx_clkout[<n>-1:0]
tx_datak[(<n>(<w>/<s>)-1:0]
rx_parallel_data[(<n><w>)-1:0]
rx_clkout[<n>-1:0]
rx_datak[<n>(<w>/<s>)-1:0]
rx_runningdisp[(<n>(<w>/<s>)-1:0]
phy_mgmt_clk
phy_mgmt_clk_reset
phy_mgmt_address[8:0]
phy_mgmt_writedata[31:0]
phy_mgmt_readdata[31:0]
phy_mgmt_write
phy_mgmt_read
phy_mgmt_waitrequest
pll_ref_clk
Deterministic PHY Top-Level Signals
tx_serial_data[<n>-1:0]
rx_serial_data[<n>-1:0]
tx_ready
rx_ready
pll_locked[<p>-1:0]
rx_bitslipboundaryselectout[(<n>5)-1:0]
tx_bitslipboundaryselect[(<n>5)-1:0]
rx_disperr[<n>(<w>/<s>)-1:0]
rx_errdetect[<n>(<w>/<s>)-1:0]
rx_syncstatus[<n>(<w>/<s>)-1:0]
rx_is_lockedtoref[<n>(<w>/<s>)-1:0]
rx_is_lockedtodata[<n>(<w>/<s>)-1:0]
rx_signaldetect[<n>(<w>/<s>)-1:0]
rx_patterndetect[(<n>(<w>/<s>)-1:0]
rx_rlv[<n>-1:0]
pll_powerdown
tx_digitalreset[<n>-1:0]
tx_analogreset[<n>-1:0]
tx_cal_busy[<n>-1:0]
rx_digitalreset[<n>-1:0]
rx_analogreset[<n>-1:0]
rx_cal_busy[<n>-1:0]
reconfig_to_xcvr[(<n>70)-1:0]
reconfig_from_xcvr[(<n>46)-1:0]
Avalon-ST Tx
from MAC
High Speed
Serial I/O
Avalon-MM PHY
Management
Interface
Reference Clock
Reset Control
and Status
(Optional)
Optional
Required
TX and RX
Status
Avalon-ST Rx
to MAC
Transceiver
Reconfiguration