User guide

9–14 Chapter 9: Deterministic Latency PHY IP Core
Interfaces
Altera Transceiver PHY IP Core March 2012 Altera Corporation
User Guide
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the Assignment Editor in Quartus II Help.
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Manual.
Interfaces
This section describes interfaces of the Deterministic Latency Transceiver PHY. It
includes the following topics:
■ Ports
■ Register Interface
■ Dynamic Reconfiguration
Ports
Figure 9–3 illustrates the top-level signals of the Deterministic Latency PHY IP core.
The variables in Figure 9–3 represent the following parameters:
■ <n>—The number of lanes
■ <w>—The width of the FPGA fabric to transceiver interface per lane
■ <s>— The symbol size