User guide

9–4 Chapter 9: Deterministic Latency PHY IP Core
Altera Transceiver PHY IP Core March 2012 Altera Corporation
User Guide
For RE
RX_latency_RE = <RX PCS latency in parallel clock cycles>
+
(<RX PMA latency in UI>
+ <PMA uncertainty reported by wordalignment_boundary[5]>)
TX_latency_RE = <TX PCS latency in parallel clock cycles>
+ <TX PMA latency in UI >
+ < Tx bitslip latency>
For REC
RX_latency_REC = <RX PCS latency in parallel clock cycles>
+ <RX PMA latency in UI> + < rx_clkout phase shift of tx_clkout>
TX_latency_REC = <TX PCS latency in parallel clock cycles>
+ <TX PMA latency in UI>
Round Trip Delay
Launch_time (from TX pins) =<clock arrival time> + <data arrival time>
= <clock arrival time>
+ <TX latency in REC> (tx bitslip=0)
= <t
PD
GPLL to CMU PLL - t
feedback
>
+ ((<TX_latency in REC> × <tx_clkout_period>)
+ t
TX_tclock_output
)
Arrival_time (at RX pins) = <latency time in RE> - <RX latency time in REC>
= (<Round_trip_latency> × <tx_clkout_period>)
– ((<RX_latency in REC> × <rx_clkout_period>)
+ <t
PDIO>RX_deser
>
+ <rx_clkout_phase_WRT_tx_clkout/360 × rx_clkout_period>)
Total Delay = <Arrival_time> – <Launch_time>
Total Delay Uncertainty
Round trip delay estimates are subject to power, voltage, and temperature (PVT)
variation.
t
RXCLK_Phase_detector_uncertainty
= 2 × max(<t
GLL_phase_step
>, <t
CDR_to_GPLL_jitter
>) + µt
SU
+ µt
H
t
Round_trip_uncertainty
= <t
RX_CLK_Phase_detector_uncertainty
+ t
GPLL->CMU PLL_variation
>
+<t
feedback_variation
> + <t
TX_tco_variation
> + <t
IO->RXdeser_delay_variation
>
+ <t
PLL_multicycle_jitter
> + <t
offset_uncertainty
>
Delay Numbers
Table 9–2 shows the total latency through the TX PCS in parallel clock cycles. The TX
compensation FIFO is in register mode.
Table 9–2. TX PCS Total Latency
Datapath Attributes
TX Phase
Comp FIFO
Serializer 8B/10B Bitslip
Total Clock
Cycles
Single word with byte serializer 1.0 0.5 0.5 0 2.0
Single word without byte serializer 1.0 1.0 2.0 0 3.0