User guide

Chapter 8: Low Latency PHY IP Core 8–15
Interfaces
March 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
Register Interface
The Avalon-MM PHY management interface provides access to the Low Latency PHY
PCS and PMA registers that control the TX and RX channels, the PMA powerdown,
PLL registers, and loopback modes. Figure 8–3 provides a high-level view of this
hardware.
Table 8–14 describes the signals in the PHY Management interface.
rx_analogreset[<n>-1:0] Input When asserted, resets the RX CDR.
rx_cal_busy[<n>-1:0] Output
When asserted, indicates that the RX channel is being calibrated. You
must hold the channel in reset until calibration completes.
Table 8–13. Avalon-ST RX Interface (Part 2 of 2)
Signal Name Direction Description
Figure 8–3. PMA
PMA and Light-Weight PCS
Dynamic
Reconfiguration
Native PMA
Control
Channel
Control
S
Avalon-MM
Control
S
Low Latency
PHY Controller
Tx Data
to Embedded
Controller
to Reconfiguration
Controller
to MAC
Tx Parallel Data
Rx Data
Rx Parallel Data
M
Avalon-MM
PHY
Mgmt
S
Rx Serial Data
Tx Serial Data
TX PLL
CMU
<n>
<n>
Table 8–14. Avalon-MM PHY Management Interface (Part 1 of 2)
Signal Name Direction Description
phy_mgmt_clk Input
Avalon-MM clock input. There is no frequency restriction for the
phy_mgmt_clk ; however, if you plan to use the same clock for the
PHY management interface and transceiver reconfiguration, you
must restrict the frequency range of
phy_mgmt_clk to
100–125 MHz to meet the specification for the transceiver
reconfiguration clock.
phy_mgmt_clk_reset Input
Global reset signal. This signal is active high and level sensitive.
This is an asynchronous signal.
phy_mgmtaddress[8:0] Input 9-bit Avalon-MM address.
phy_mgmt_writedata[31:0] Input Input data.
phy_mgmt_readdata[31:0] Output Output data.