User guide

Chapter 1: Introduction 1–5
Unsupported Features
March 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
The Verilog and VHDL transceiver PHY IP cores have been tested with the following
simulators:
■ ModelSim SE
■ Synopsys VCS MX
■ Cadence NCSim
If you select VHDL for your transceiver PHY, only the wrapper generated by the
Quartus II software is in VHDL. All the underlying files are written in Verilog or
System Verilog. To enable simulation using a VHDL-only ModelSim license, the
underlying Verilog and System Verilog files for the transceiver PHY are encrypted so
that they can be used with the top-level VHDL wrapper without using a
mixed-language simulator.
f For more information about simulating with ModelSim, refer to the Mentor Graphics
ModelSim Support chapter in volume 3 of the Quartus II Handbook
1 The transceiver PHY IP cores do not support the NativeLink feature in the Quartus II
software.
Unsupported Features
The protocol-specific PHYs are not supported in SOPC Builder or Qsys in the current
release.
<project_dir>/<instance_name>_sim/cadence Simulation file for Cadence simulation tools.
<project_dir>/<instance_name>_sim/mentor Simulation file for Mentor simulation tools.
<project_dir>/<instance_name>_sim/synopsys Simulation file for Synopsys simulation tools.
Table 1–2. Generated Files (Part 2 of 2)
File Name Description