User guide

8–2 Chapter 8: Low Latency PHY IP Core
Performance and Resource Utilization
Altera Transceiver PHY IP Core March 2012 Altera Corporation
User Guide
Table 8–1 shows the level of support offered by the PMA IP core for Altera device
families.
Performance and Resource Utilization
Table 8–2 shows the typical expected device resource utilization for different
configurations using the current version of the Quartus II software targeting a
Stratix V GX (5SGSMD612H35C2) device.
.
Table 8–1. Device Family Support
Device Family Support
Stratix V devices Preliminary
Other device families No support
Table 8–2. Low Latency PHY Performance and Resource Utilization—Stratix V GX Device
Implementation
Number of
Lanes
Serialization
Factor
Worst-Case
Frequency
Combinational
ALUTs
Dedicated
Registers
Memory
Bits
11 Gbps 1 32 or 40 599.16 112 95 0
11 Gbps 4 32 or 40 584.8 141 117 0
11 Gbps 10 32 or 40 579.71 192 171 0
6 Gbps (10 Gbps
datapath)
1 32 or 40 608.27 111 93 0
6 Gbps (10 Gbps
datapath)
4 32 or 40 454.96 141 117 0
6 Gbps (10 Gbps
datapath)
10 32 or 40 562.75 192 171 0
6 Gbps (8 Gbps
datapath)
1 32 or 40 607.16 113 93 0
6 Gbps (8 Gbps
datapath)
4 32 or 40 639.8 142 117 0
6 Gbps (8 Gbps
datapath)
10 32 or 40 621.89 193 171 0
3 Gbps (8 Gbps
datapath)
1 8, 10, 16, or 20 673.4 114 93 0
3 Gbps (8 Gbps
datapath)
4 8, 10, 16, or 20 594.88 142 117 0
3 Gbps (8 Gbps
datapath)
10 8, 10, 16, or 20 667.67 193 171 0