User guide

March 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
8. Low Latency PHY IP Core
The Altera Low Latency PHY IP core receives and transmits differential serial data,
recovering the RX clock from the RX input stream. The PMA connects to a simplified
PCS whose single function doubles the width of the TX and RX datapaths. Depending
on the configuration you choose, the Low Latency PHY IP core instantiates one the
following the channels:
■ GX channels using the Standard PCS with a frequency range of 1–8.5 Gbps
■ GX channels using the 10G PCS with a frequency range of 1–12.5 Gbps
■ GT channels in PMA-Direct mode with a maximum frequency of 20–28 Gbps. The
maximum frequency for Stratix V ES silicon is 26 Gbps.
An Avalon-ST interface is used for TX and RX data for the MAC interface. An
Avalon-MM interface provides access to control and status information.
Figure 8–1 illustrates the top-level modules of the Low Latency PHY IP core.
Because the Low latency PHY IP core bypasses much of the PCS, it minimizes the PCS
latency.
f For more detailed information about the Low Latency datapath and clocking, refer to
the refer to the “Stratix V GX Device Configurations” section in the Transceiver
Configurations in Stratix V Devices chapter of the Stratix V Device Handbook.
Device Family Support
IP cores provide either final or preliminary support for target Altera device families.
These terms have the following definitions:
■ Final support—Verified with final timing models for this device.
■ Preliminary support—Verified with preliminary timing models for this device.
Figure 8–1. Low-Latency PHY IP Core—Stratix V Devices
Tx serial data
Rx serial data
Stratix V FPGA
PMA
PCS
Phase Comp
Byte Serializer
Avalon-MM
Control & Status
Avalon-ST
to
MAC
to
Embedded
Controller