User guide

Chapter 7: Custom PHY IP Core 7–15
Interfaces
March 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
Interfaces
This section describes interfaces of the Custom Transceiver PHY. It includes the
following topics:
■ Ports
■ Register Interface
■ Dynamic Reconfiguration
Ports
Figure 7–2 illustrates the top-level signals of the Custom PHY IP core. The variables in
Figure 7–2 represent the following parameters:
Enable manual disparity control Off
Create optional 8B/10B status port Off
Word Aligner Options
Word alignment mode Automatic synchronization state machine
Number of consecutive valid words before sync
state is reached
1
Number of bad data words before loss of sync
state
1
Number of valid patterns before sync state is
reached
10
Create optional word aligner status ports Off
Word aligner patte
rn length 10
Word alignment pattern 1011111100
Enable run length violation checking Off
Run length 40
Rate Match Options
Enable rate match FIFO On
Rate match insertion/deletion +ve disparity
pattern
10100010010101111100
Rate match insertion/deletion -ve disparity
pattern
10101011011010000011
Byte Order Options
Enable byte ordering block Off
Enable byte ordering block manual control Off
Byte ordering patt
ern 1111111011
Byte ordering pad pattern N/A
Datapath
Deserializer block width Auto
Table 7–13. Presets for the 1.25GbE Protocol
Parameter Name 1.25GbE