User guide

7–14 Chapter 7: Custom PHY IP Core
Parameter Settings
Altera Transceiver PHY IP Core March 2012 Altera Corporation
User Guide
h For more information about the Pin Planner, refer to About the Pin Planner in
Quartus II Help. For more information about the Assignment Editor, refer to About
the Assignment Editor in Quartus II Help.
f For more information about Quartus II Settings, refer to Quartus II Settings File
Manual.
Presets for Ethernet
If you apply the presets for 1.25GbE, parameters with specific required values for
those protocols are set for you. Once applied, the preset is in boldface and remains as
such unless you change some of the preset parameters. Selecting a preset does not
prevent you from changing any parameter to meet the requirements of your design.
Table 7–13 lists the parameters that are set for the 1.25GbE protocol.
XCVR_TX_VOD
Transmitter Differential
Output Voltage
Differential output voltage setting. The
values are monotonically increasing
with the driver main tap current
strength.
0–63
50
Pin
XCVR_TX_VOD_PRE_EMP_
CTRL_SRC
Transmitter V
OD
/
Preemphasis Control
Source
When set to
DYNAMIC_CTL , the PCS
block controls the V
OD
and
preemphasis coefficients for PCI
Express. When this assignment is set
to
RAM_CTL the V
OD
and preemphasis
are controlled by other assignments,
such as
XCVR_TX_PRE_EMP_1ST_POST_TAP .
DYNAMIC_CTL
RAM_CTL
Pin
Table 7–12. Transceiver and PLL Assignments for Stratix V Devices (Sheet 1 of 3)
QSF Assignment Name
Pin Planner and
Assignment Editor
Name
Description Options Assign To
Table 7–13. Presets for the 1.25GbE Protocol
Parameter Name 1.25GbE
General Options Tab
Transceiver Protocol GbE
Enable bonding Off
FPGA fabric transceiver interface width 8
Data rate 1250 Mbps
Input clock frequency 125 MHz
Enable TX Bitslip Off
Create rx_coreclkin port Off
Create tx_coreclkin port Off
Create optional ports Off
8B/10B Options
Enable 8B/10B decoder/encoder On