User guide
7–8 Chapter 7: Custom PHY IP Core
Parameter Settings
Altera Transceiver PHY IP Core March 2012 Altera Corporation
User Guide
8B/10B Encoder and Decoder
The 8B/10B encoder generates 10-bit code groups (control or data word) with proper
disparity from the 8-bit data and 1-bit control identifier. The 8B/10B decoder receives
10-bit data from the rate matcher and decodes it into an 8-bit data and 1-bit control
identifier. Table 7–8 lists the settings available on the 8B/10B tab.
Byte Ordering
The byte ordering block is available when the PCS width is doubled at the byte
deserializer. Byte ordering identifies the first byte of a packet by determining whether
the programmed start-of-packet (SOP) pattern is present; it inserts enough pad
characters in the data stream to force the SOP to the lowest order byte lane. Table 7–9
describes the byte order options.
1 You cannot enable Rate Match FIFO when your application requires byte ordering.
Because the rate match function inserts and deletes idle characters, it may shift the
SOP to a different byte lane.
Rate match
insertion/deletion -ve
disparity pattern
0010111100
0101111100
Enter a 10-bit skip pattern (bits 10–19) and a 10-bit control pattern
(bits 0–9). The skip pattern must have neutral disparity.
Create optional rate match
FIFO status ports
On/Off
When enabled, creates the
rx_rmfifoddatainserted
and
rx_rmfifodatadeleted
signals from the rate match FIFO become
output ports.
Table 7–7. Rate Match FIFO Options (Part 2 of 2)
Name Value Description
Table 7–8. 8B/10B Options
Name Value Description
Enable 8B/10B decoder/encoder On/Off
Enable this option if your application requires 8B/10B encoding and
decoding. This option on adds the
tx_datak
<n>,
rx_datak
<n>,
and
rx_runningdisp
<n> signals to your transceiver.
Enable manual disparit y control On/Off
When enabled, you can use the
tx_forcedisp
signal to control the
disparity of the 8B/10B encoder. Turning this option on adds the
tx_forcedisp
and
tx_dispval
signals to your transceiver.
Create optional 8B/10B status
port
On/Off
Enable this option to include the 8B/10B
rx_errdetect
and
rx_disperr
error signals at the top level of the Custom PHY IP
core.
Table 7–9. Byte Order Options
Name Value Description
Enable byte ordering block On/Off
Turn this option on if your application uses serialization to create a
datapath that is larger than 1 symbol. This option is only available if
you use the byte deserializer.
Enable byte ordering block
manual control
On/Off
Turn this option on to choose manual control of byte ordering. This
option creates the
rx_enabyteord
signal. A byte ordering operation
occurs whenever
rx_enabyteord
is asserted. To perform multiple
byte ordering operations, deassert and reassert
rx_enabyteord
.