User guide

7–2 Chapter 7: Custom PHY IP Core
Device Family Support
Altera Transceiver PHY IP Core March 2012 Altera Corporation
User Guide
Figure 7–1 illustrates the top-level signals and modules of the Custom PHY.
f For more detailed information about the Custom datapath and clocking, refer to the
“Custom Configurations with the Standard PCS” section in the Transceiver Custom
Configurations in Stratix V Devices chapter of the Stratix V Device Handbook.
Device Family Support
IP cores provide either final or preliminary support for target Altera device families.
These terms have the following definitions:
■ Final support—Verified with final timing models for this device.
■ Preliminary support—Verified with preliminary timing models for this device.
Table 7–1 shows the level of support offered by the Custom PHY IP core for Altera
device families.
Performance and Resource Utilization
Because the PCS and PMA are both implemented in hard logic, the Custom PHY IP
core requires less than 1% of FPGA resources. Table 7–1 lists the resource utilization
for the Custom PHY when the 1.25GbE preset is specified.
Figure 7–1. Custom PHY IP Core
Custom PHY IP Core
Tx Serial Data
Avalon-ST Tx and Rx
Rx Serial Data
to
ASIC,
ASSP,
FPGA,
or
Backplane
from
Custom
MAC
Stratix V FPGA
PCS:
8B/10B
Word Aligner
Rate Match FIFO
Byte Ordering
PMA:
Analog Buffers
SERDES
Avalon-MM Cntrl and Status
Avalon-ST Reconfig
Table 7–1. Device Family Support
Device Family Support
Stratix V devices–Hard PCS and PMA Preliminary
Arria V devices–Hard PCS and PMA Preliminary
Cyclone V devices–Hard PCS and PMA Preliminary
Other device families No support
Table 7–2. Custom PHY IP Core Performance and Resource Utilization—Stratix V GT Device
Channels Combinational ALUTs Logic Registers (Bits)
1 142 154
4 244 364