User guide

March 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
7. Custom PHY IP Core
The Altera Custom PHY IP core is a generic PHY that you can customize for use in
Arria V or Stratix V FPGAs. You can connect your application’s MAC-layer logic to
the Custom PHY to transmit and receive data at rates of 0.611–6.5536 Gbps for Arria V
devices or 0.622–8.5 Gbps for Stratix V devices. You can parameterize the physical
coding sublayer (PCS) to include the functions that your application requires. The
following functions are available:
■ 8B/10B encode and decode
■ Three word alignment modes
■ Rate matching
■ Byte ordering
By setting the appropriate options using the parameter editor, you can configure the
Custom PHY IP core to support many standard protocols, including all of the
following protocols:
■ Serial Data Converter (SDC(JESD204A))
■ Serial digital interface (SDI)
■ Ethernet (GbE)
■ Serial RapidIO
®
(SRIO) 1.3
■ Serial ATA (SATA) and sequential active serial (SAS) Gen1, Gen2, and Gen3
■ Gigabit-capable passive optical network (GPON)
Your MAC layer must use the Avalon-ST to transmit and receive data from the
Custom PHY. The Avalon-ST protocol is a simple protocol designed for driving high
bandwidth, low latency, unidirectional data. To access control and status registers in
the Custom PHY, your design must include an embedded controller with an
Avalon-MM master interface. This is a standard, memory-mapped protocol that is
typically used to read and write registers and memory.
f For more information about the Avalon-ST and Avalon-MM protocols, refer to the
Avalon Interface Specifications.