Specifications

1–24 Chapter 1: Nios II Hardware Development
Creating the Design Example
Nios II Hardware Development Tutorial May 2011 Altera Corporation
4. Type first_nios2_system in the File name box and click Save. The Generate
dialog box appears and system generation process begins.
The generation process can take several minutes. Output messages appear as
generation progresses. When generation completes, the final "Info: Finished:
Create HDL design files for synthesis" message appears. Figure 1–13 shows the
successful system generation.
5. Click Close to close the dialog box.
6. On the File menu, click Exit to close Qsys and return to the Quartus II software.
Congratulations! You have finished creating the Nios II processor system. You are
ready to integrate the system into the Quartus II hardware project and use the Nios II
SBT for Eclipse to develop software.
f For more information about generating systems with Qsys, refer to the System Design
with Qsys section of Volume 1: Design and Synthesis of the Quartus II Handbook. For
information about hardware simulation for Nios II systems, refer to Simulating Nios II
Embedded Processor Designs.
Integrate the Qsys System into the Quartus II Project
In this section you perform the following steps to complete the hardware design:
■ Instantiate the Qsys system module in the Quartus II project.
■ Assign FPGA device and pin locations.
Figure 1–13. Successful System Generation