Nios II Hardware Development Tutorial Nios II Hardware Development Tutorial 101 Innovation Drive San Jose, CA 95134 www.altera.com TU-N2HWDV-4.
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Contents Chapter 1. Nios II Hardware Development Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 Software and Hardware Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 OpenCore Plus Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iv Nios II Hardware Development Tutorial Contents May 2011 Altera Corporation
1. Nios II Hardware Development This tutorial introduces you to the system development flow for the Nios® II processor. Using the Quartus® II software and the Nios II Embedded Design Suite (EDS), you build a Nios II hardware system design and create a software program that runs on the Nios II system and interfaces with components on Altera® development boards. The tutorial is a good starting point if you are new to the Nios II processor or the general concept of building embedded systems in FPGAs.
1–2 Chapter 1: Nios II Hardware Development Software and Hardware Requirements Figure 1–1 is a block diagram showing the relationship among the host computer, the target board, the FPGA, and the Nios II system. Figure 1–1.
Chapter 1: Nios II Hardware Development OpenCore Plus Evaluation 1–3 You can build the design example in this tutorial with any Altera development board or your own custom board that meets the following requirements: 1 ■ The board must have an Altera Stratix® series, Cyclone® series, or Arria® series FPGA. ■ The FPGA must contain a minimum of 2500 logic elements (LE) or adaptive lookup tables (ALUT). ■ The FPGA must contain a minimum of 50 M4K or M9K memory blocks.
1–4 Chapter 1: Nios II Hardware Development Nios II System Development Flow Nios II System Development Flow This section discusses the complete design flow for creating a Nios II system and prototyping it on a target board. Figure 1–2 shows the Nios II system development flow. Figure 1–2.
Chapter 1: Nios II Hardware Development Nios II System Development Flow 1–5 Analyzing System Requirements The development flow begins with predesign activity which includes an analysis of the application requirements, such as the following questions: ■ What computational performance does the application require? ■ How much bandwidth or throughput does the application require? ■ What types of interfaces does the application require? ■ Does the application require multithreaded software? Based on th
1–6 Chapter 1: Nios II Hardware Development Nios II System Development Flow f For more information about the following topics, refer to the related documentation: ■ For Nios II processor cores, refer to the Nios II Processor Reference Handbook. ■ For Qsys and developing custom components, refer to the System Design with Qsys section of Volume 1: Design and Synthesis of the Quartus II Handbook. ■ For custom instructions, refer to the Nios II Custom Instruction User Guide.
Chapter 1: Nios II Hardware Development Nios II System Development Flow 1–7 ■ Hexadecimal (Intel-Format) File (.hex)—Contains initialization information for on-chip memories. The Nios II SBT for Eclipse generate these initialization files for on-chip memories that support initialization of contents. ■ Flash memory programming data—Is boot code and other arbitrary data you might write to flash memory.
1–8 Chapter 1: Nios II Hardware Development Creating the Design Example f Altera provides several working Nios II reference designs which you can use as a starting point for your own designs. After installing the Nios II EDS, refer to the /examples/verilog or the / examples/vhdl directory. Demonstration applications are also available in newer development kit installations.
Chapter 1: Nios II Hardware Development Creating the Design Example 1–9 Perform the following steps to set up the design environment: 1. Locate the zipped design files on the Altera web site. 2. Unzip the contents of the zip file to a directory on your computer. Do not use spaces in the directory path name. The remainder of this tutorial refers to this directory as the . Analyze System Requirements This section describes the system requirements for the tutorial design example.
1–10 Chapter 1: Nios II Hardware Development Creating the Design Example To open the Quartus II project, perform the following steps: 1. Start the Quartus II software. On Windows computers, click Start, point to Programs, Altera, Quartus II , and then click Quartus II . On Linux computers, type quartus at a shell command prompt, assuming the Quartus II program directory is in the search path. 2. Click Open Existing Project on the splash screen, or, on the File menu, click Open Project.
Chapter 1: Nios II Hardware Development Creating the Design Example 1–11 Figure 1–4 shows the Qsys GUI in its initial state. Figure 1–4. Qsys GUI Define the System in Qsys You use Qsys to define the hardware characteristics of the Nios II system, such as which Nios II core to use, and what components to include in the system. Qsys does not define software behavior, such as where in memory to store instructions or where to send the stderr character stream.
1–12 Chapter 1: Nios II Hardware Development Creating the Design Example Perform the following steps: 1. On the Project Settings tab, select the Device Family that matches the Altera FPGA you are targeting. 1 If a warning appears stating the selected device family does not match the Quartus project settings, ignore the warning. You specify the device in the Quartus project settings later in this tutorial. 2.
Chapter 1: Nios II Hardware Development Creating the Design Example 1–13 Figure 1–5 shows the On-Chip Memory (RAM or ROM) parameter editor. Figure 1–5. On-Chip Memory Parameter Editor 5. Click Finish. You return to Qsys. 6. Click the System Contents tab. An instance of the on-chip memory appears in the system contents table. 1 For more information about on-chip memory, you can click Documentation in the On-Chip Memory (RAM or ROM) parameter editor.
1–14 Chapter 1: Nios II Hardware Development Creating the Design Example 1 You must type these tutorial component names exactly as specified. Otherwise, the tutorial programs written for this Nios II system fail in later steps. In general, it is a good habit to give descriptive names to hardware components. Nios II programs use these symbolic names to access the component hardware. Therefore, your choice of component names can make Nios II programs easier to read and understand.
Chapter 1: Nios II Hardware Development Creating the Design Example 1–15 Figure 1–6 shows the Core Nios II tab of the Nios II Processor parameter editor. Figure 1–6. Nios II Parameter Editor – Core Nios II Tab 15. Click the Caches and Memory Interfaces tab. Figure 1–7 shows the GUI. 16. In the Instruction cache list, select 2 Kbytes. 17. In the Burst transfers list, select Disable. 18. In the Number of tightly coupled instruction master port(s) list, select None.
1–16 Chapter 1: Nios II Hardware Development Creating the Design Example Figure 1–7 shows the Caches and Memory Interfaces tab of the Nios II Processor parameter editor. Figure 1–7. Nios II Parameter Editor – Caches and Memory Interfaces Tab 1 Do not change any settings on the Advanced Features, MMU and MPU Settings, JTAG Debug Module, or Custom Instruction tabs. 19. Click Finish. You return to the Qsys System Contents tab.
Chapter 1: Nios II Hardware Development Creating the Design Example 1–17 Add the JTAG UART The JTAG UART provides a convenient way to communicate character data with the Nios II processor through the USB-Blaster download cable. Perform the following steps to add the JTAG UART: 1. On the Component Library tab, expand Interface Protocols, expand Serial, and then click JTAG UART. 2. Click Add. The JTAG UART parameter editor appears. 1 Do not change the default settings.
1–18 Chapter 1: Nios II Hardware Development Creating the Design Example 7. Connect the clk_reset port of the clk_0 clock source to the reset port of the JTAG UART. 8. Connect the data_master port of the Nios II processor to the avalan_jtag_slave port of the JTAG UART. 1 The instruction_master port of the Nios II processor does not connect to the JTAG UART because the JTAG UART is not a memory device and cannot send instructions to the Nios II processor.
Chapter 1: Nios II Hardware Development Creating the Design Example 1–19 Figure 1–9 shows the Interval Timer parameter editor. Figure 1–9. Interval Timer Parameter Editor 4. Click Finish. You return to the Qsys System Contents tab, and an instance of the interval timer appears in the system contents table. 5. In the Name column, right-click the interval timer and click Rename. 6. Type sys_clk_timer and press Enter. 7. Connect the clk port of the clk_0 clock source to the clk port of the interval timer.
1–20 Chapter 1: Nios II Hardware Development Creating the Design Example Perform the following steps to add the system ID peripheral: 1. On the Component Library tab, expand Peripherals, expand Debug and Performance, and then click System ID Peripheral. 2. Click Add. The System ID Peripheral parameter editor appears. 1 Do not change the default setting. Figure 1–10 shows the System ID Peripheral parameter editor. Figure 1–10. System ID Peripheral Parameter Editor 3. Click Finish.
Chapter 1: Nios II Hardware Development Creating the Design Example 1–21 1. On the Component Library tab, expand Peripherals, expand Microcontroller Peripherals, and then click PIO (Parallel I/O). 2. Click Add. The PIO (Parallel I/O) parameter editor appears. Figure 1–11 shows the GUI. 1 Do not change the default settings. The parameter editor defaults to an 8-bit outputonly PIO, which exactly matches the needs for the design example. Figure 1–11 shows the PIO (Parallel I/O) parameter editor.
1–22 Chapter 1: Nios II Hardware Development Creating the Design Example 7. Connect the clk_reset port of the clk_0 clock source to the reset port of the PIO. 8. Connect the data_master port of the Nios II processor to the s1 port of the PIO. 9. In the external_connection row, click Click to export in the Export column to export the PIO ports. f For more information about the PIO, refer to the PIO Core chapter in the Embedded Peripherals IP User Guide.
Chapter 1: Nios II Hardware Development Creating the Design Example 1–23 5. Click the IRQ value for the sys_clk_timer component to select it. 6. Type 1 and press Enter to assign a new IRQ value. Figure 1–12 shows the Qsys System Contents tab with the complete system. Figure 1–12. System Contents Tab with Complete System Generate the Qsys System You are now ready to generate the Qsys system. Perform the following steps: 1. Click the Generation tab. 2.
1–24 Chapter 1: Nios II Hardware Development Creating the Design Example 4. Type first_nios2_system in the File name box and click Save. The Generate dialog box appears and system generation process begins. The generation process can take several minutes. Output messages appear as generation progresses. When generation completes, the final "Info: Finished: Create HDL design files for synthesis" message appears. Figure 1–13 shows the successful system generation. Figure 1–13.
Chapter 1: Nios II Hardware Development Creating the Design Example ■ Compile the Quartus II project. ■ Verify timing. 1–25 f For further information about using the Quartus II software, refer to Introduction to the Quartus II Software, the Quartus II Handbook, and the Quartus II Software Interactive Tutorial in the Training section of the Altera website. Instantiate the Qsys System Module in the Quartus II Project Qsys outputs a design entity called the system module.
1–26 Chapter 1: Nios II Hardware Development Creating the Design Example Figure 1–14 shows the completed .bdf schematic using the LED pins. Figure 1–14. Completed Board Design File Schematic Add IP Variation File In this section, you add the Quartus II IP File (.qip) to the your Quartus II project. To add the .qip, perform the following steps: 1. On the Assignments menu, click Settings. The Settings dialog box appears. 2. Under Category, click Files. The Files page appears. 3.
Chapter 1: Nios II Hardware Development Creating the Design Example 1–27 2. In the Family list, select the FPGA family that matches your board. 1 If prompted to remove location assignments, do so. 3. Under Target device, select Specific device selected in 'Available devices' list. 4. Under Available devices, select the exact device that matches your board. 1 If prompted to remove location assignments, do so. 5. Click OK to accept the device assignment.
1–28 Chapter 1: Nios II Hardware Development Creating the Design Example 5. In the PLD_CLOCKINPUT row, double-click in the Location cell to access a list of available pin locations. Figure 1–16 shows the GUI. Figure 1–16. Assigning Pins with the Quartus II Pin Planner 6. Select the appropriate FPGA pin that connects to the oscillator on the board. 1 If your design fails to work, recheck your board documentation for this step first. 7.
Chapter 1: Nios II Hardware Development Creating the Design Example 1–29 Figure 1–17 shows the Unused Pins page of the Device and Pin Options dialog box. Figure 1–17. The Unused Pins Page of the Device and Pin Options Dialog Box 14. In the Reserve all unused pins list, select As input tri-stated with weak pull-up. With this setting, all unused I/O pins on the FPGA enter a high-impedance state after power-up.
1–30 Chapter 1: Nios II Hardware Development Creating the Design Example To ensure the design meets timing, perform the following steps: 1. On the File menu, click Open. 2. In the Files of type list, select Script Files (*.tcl, *.sdc, *.qip). 3. Browse to locate /hw_dev_tutorial.sdc and click Open. The file opens in the text editor. 4. Locate the following create_clock command: create_clock -name sopc_clk -period 20 [get_ports PLD_CLOCKINPUT] 5.
Chapter 1: Nios II Hardware Development Creating the Design Example 1–31 11. Click Add to include hw_dev_tutorial.sdc in the project. 12. Turn on Enable multicorner timing analysis during compilation. 13. Click OK. To compile the Quartus II project, perform the following steps: 1. On the Processing menu, click Start Compilation. The Tasks window and percentage and time counters in the lower-right corner display progress. The compilation process can take several minutes.
1–32 Chapter 1: Nios II Hardware Development Creating the Design Example f For information about download cables and drivers, refer to the Download Cables page of the Altera website. 5. Click Close. 6. In the nios2_quartus2_project.sof row, turn on Program/Configure. 7. Click Start. The Progress meter sweeps to 100% as the Quartus II software configures the FPGA. At this point, the Nios II system is configured and running in the FPGA, but it does not yet have a program in memory to execute.
Chapter 1: Nios II Hardware Development Creating the Design Example 1–33 4. On the File menu, point to New, and then click Nios II Application and BSP from Template. The Nios II Application and BSP from Template wizard appears. Figure 1–20 shows the GUI. Figure 1–20. Nios II Application and BSP from Template Wizard 5. Under Target hardware information, next to SOPC Information File name, browse to locate the . 6. Select first_nios2_system.sopcinfo and click Open.
1–34 Chapter 1: Nios II Hardware Development Creating the Design Example Compile the Project In this section you compile the project to produce an executable software image. For the tutorial design example, you must first adjust the project settings to minimize the memory footprint of the software, because your Nios II hardware system contains only 20 KB of memory. Perform the following steps: 1. In the Project Explorer view, right-click count_binary_bsp and click Properties.
Chapter 1: Nios II Hardware Development Creating the Design Example 1–35 4. Click OK. The BSP regenerates, the Properties dialog box closes, and you return to the Nios II SBT for Eclipse. 5. In the Project Explorer view, right-click the count_binary project and click Build Project. The Build Project dialog box appears, and the Nios II SBT for Eclipse begins compiling the project. When compilation completes, a "count_binary build complete" message appears in the Console view.
1–36 Chapter 1: Nios II Hardware Development Taking the Next Step Taking the Next Step Congratulations! You have completed building a Nios II hardware system and running software on it.
Additional Information This chapter provides additional information about the document and Altera. Document Revision History The following table shows the revision history for this document. f Refer to the Nios II Embedded Design Suite Release Notes page of the Altera website for the latest features, enhancements, and known issues in the current release. Date Version Changes May 2011 4.0 Revised entire document to use Qsys. December 2009 3.
Info–2 Additional Information Typographic Conventions Typographic Conventions The following table shows the typographic conventions this document uses. Visual Cue Meaning Bold Type with Initial Capital Letters Indicate command names, dialog box titles, dialog box options, and other GUI labels. For example, Save As dialog box. For GUI elements, capitalization matches the GUI.
