Specifications

Bit-31 cache bypass is only provided in the Nios II/f core, and must not be used with other Nios II cores.
The other Nios II cores limit their maximum byte address space to 31 bits to ease migration of code from
one implementation to another. They effectively ignore the value of bit 31, which allows code written for a
Nios II/f core using bit 31 cache bypass to run correctly on other current Nios II implementations. In
general, this feature depends on the Nios II core implementation.
For more information, refer to the "Nios II Core Implementation Details" chapter of the Nios II Processor
Reference Handbook.
Related Information
Nios II Core Implementation Details
For HAL Users
The HAL provides the C-language IORD_*DIRECT macros that expand to the ldio family of instructions
and the IOWR_*DIRECT macros that expand to the stio family of instructions.
For more information, refer to the "HAL I/O Macros to Bypass the Data Cache" table (Table 9-1).
These macros are provided to access noncacheable memory regions.
The HAL provides the alt_uncached_malloc(), alt_uncached_free(), alt_remap_uncached(), and
alt_remap_cached() routines to allocate and manipulate regions of uncached memory. These routines
are available on Nios II cores with or without a data cache—code written for a Nios II core with a data
cache is completely compatible with a Nios II core without a data cache.
The alt_uncached_malloc() and alt_remap_uncached() routines guarantee that the allocated memory
region is not in the data cache and that all subsequent accesses to the allocated memory regions bypass the
data cache.
Nios II Tightly-Coupled Memory
If you want the performance of cache all the time, place your code or data in a tightly-coupled memory.
Tightly-coupled memory is fast on-chip memory that bypasses the cache and has guaranteed low latency.
Tightly-coupled memory gives the best memory access performance. You assign code and data to tightly-
coupled memory partitions in the same way as other memory sections.
Cache instructions do not affect tightly-coupled memory. However, cache-management instructions
become NOPs, which might result in unnecessary overhead.
For more information, refer to “Memory Usage” in the "Developing Programs Using the Hardware
Abstraction Layer" chapter of the Nios II Software Developer’s Handbook.
Related Information
Developing Programs Using the Hardware Abstraction Layer on page 6-1
Document Revision History for Cache and Tightly-Coupled Memory
Date Version Changes
May 2015 2015.05.14
• Maintenance release.
• Renamed to Nios II Classic.
9-6
For HAL Users
NII5V2
2015.05.14
Altera Corporation
Cache and Tightly-Coupled Memory
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