Specifications

For HAL Users
The HAL provides the C-language macros IORD and IOWR that expand to the appropriate assembly
instructions to bypass the data cache. The IORD macro expands to the ldwio instruction, and the IOWR
macro expands to the stwio instruction. These macros are provided to enable HAL device drivers to
access device registers.
All of these macros bypass the data cache when they perform their operation. In general, your program
passes values defined in system.h as the BASE and REGNUM parameters. These macros are defined in the file
<Nios II EDS install path>/components/altera_nios2/HAL/inc/io.h.
Table 9-1: HAL I/O Macros to Bypass the Data Cache
Macro Use
IORD(BASE, REGNUM) Read the value of the register at offset REGNUM in a
device with base address BASE. Registers are
assumed to be offset by the address width of the
bus.
IOWR(BASE, REGNUM, DATA) Write the value DATA to the register at offset
REGNUM in a device with base address BASE.
Registers are assumed to be offset by the address
width of the bus.
IORD_32DIRECT(BASE, OFFSET) Make a 32-bit read access at the location with
address BASE+OFFSET.
IORD_16DIRECT(BASE, OFFSET) Make a 16-bit read access at the location with
address BASE+OFFSET.
IORD_8DIRECT(BASE, OFFSET) Make an 8-bit read access at the location with
address BASE+OFFSET.
IOWR_32DIRECT(BASE, OFFSET, DATA) Make a 32-bit write access to write the value DATA
at the location with address BASE+OFFSET.
IOWR_16DIRECT(BASE, OFFSET, DATA) Make a 16-bit write access to write the value DATA
at the location with address BASE+OFFSET.
IOWR_8DIRECT(BASE, OFFSET, DATA) Make an 8-bit write access to write the value DATA
at the location with address BASE+OFFSET.
Cache Considerations for Writing Program Loaders
Software that writes instructions to memory, such as program loaders, needs to ensure that old instruc‐
tions are flushed from the instruction cache and processor pipeline. This flushing is accomplished with
the flushi and flushp instructions, respectively. Additionally, if new instruction(s) are written to
memory using store instructions that do not bypass the data cache, you must use the flushd instruction
to flush the new instruction(s) from the data cache to memory.
Example 9–4. Assembly Code That Writes a New Instruction to Memory
/*
* Assume new instruction in r4 and
* instruction address already in r5.
*/
9-4
For HAL Users
NII5V2
2015.05.14
Altera Corporation
Cache and Tightly-Coupled Memory
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