Specifications
Assembly Code to Initialize the Instruction Cache
Place the initi instruction in a loop that executes initi for each instruction cache line address.
Example 9–2. Assembly Code to Initialize the Instruction Cache
mov r4, r0
movhi r5, %hi(NIOS2_ICACHE_SIZE)
ori r5, r5, %lo(NIOS2_ICACHE_SIZE)
icache_init_loop:
initi r4
addi r4, r4, NIOS2_ICACHE_LINE_SIZE
bltu r4, r5, icache_init_loop
After the instruction cache is initialized, the data cache must also be initialized. The Nios II initd instruc‐
tion initializes a single data cache line. Do not use the flushd instruction for this purpose, because it
writes dirty lines back to memory. The data cache is undefined after reset, including the cache line tags.
Using flushd can cause unexpected writes of random data to random addresses. The initd instruction
does not write back dirty data.
Assembly Code to Initialize the Data Cache
Example 9–3. Assembly Code to Initialize the Data Cache
mov r4, r0
movhi r5, %hi(NIOS2_DCACHE_SIZE)
ori r5, r5, %lo(NIOS2_DCACHE_SIZE)
dcache_init_loop:
initd 0(r4)
addi r4, r4, NIOS2_DCACHE_LINE_SIZE
bltu r4, r5, dcache_init_loop
Note:
Place the initd instruction in a loop that executes initd for each data cache line address.
It is legal to execute instruction and data cache initialization code on Nios II cores that do not implement
one or both of the caches. The initi and initd instructions are simply treated as nop instructions if there
is no cache of the corresponding type present.
For HAL Users
Programs based on the HAL need not manage the initialization of cache memory. The HAL C run-time
code (crt0.S) provides a default reset handler that performs cache initialization before alt_main() or
main() is called.
Nios II Device Driver Cache Considerations
Device drivers typically access control registers associated with their device. These registers are mapped
into the Nios II address space. When accessing device registers, the data cache must be bypassed to ensure
that accesses are not lost or deferred due to the data cache.
When writing a device driver, bypass the data cache with the ldio/stio family of instructions. On Nios II
cores without a data cache, these instructions behave just like their corresponding ld/st instructions, and
therefore are benign.
Note:
Declaring a C pointer volatile does not make pointer accesses bypass the data cache. The
volatile keyword merely prevents the compiler from optimizing out accesses using the pointer.
This volatile behavior is different from the methodology for the first-generation Nios processor.
NII5V2
2015.05.14
Assembly Code to Initialize the Instruction Cache
9-3
Cache and Tightly-Coupled Memory
Altera Corporation
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