Specifications

Related Information
Nios II Core Implementation Details
Defining Cache Properties
The details for a particular Nios II processor system are defined in the system.h file.
Example 9–1. An Excerpt from system.h that Defines the Cache Structure
#define NIOS2_ICACHE_SIZE 4096
#define NIOS2_DCACHE_SIZE 0
#define NIOS2_ICACHE_LINE_SIZE 32
#define NIOS2_DCACHE_LINE_SIZE 0
This system has a 4 KB instruction cache with 32 byte lines, and no data cache.
HAL API Functions for Managing Cache
The HAL application program interface (API) provides the following functions for managing cache
memory:
• alt_dcache_flush()
• alt_dcache_flush_no_writeback()
• alt_dcache_flush_all()
• alt_icache_flush()
• alt_icache_flush_all()
• alt_uncached_malloc()
• alt_uncached_free()
• alt_remap_uncached()
• alt_remap_cached()
For more information about API functions, refer to the "HAL API Reference" chapter of the Nios II
Software Developer’s Handbook.
Related Information
HAL API Reference on page 14-1
Initializing the Nios II Cache after Reset
After reset, the contents of the instruction cache and data cache are unknown. They must be initialized at
the start of the software reset handler for correct operation.
The Nios II caches cannot be disabled by software; they are always enabled. To allow proper operation, a
processor reset causes the instruction cache to invalidate the one instruction cache line that corresponds
to the reset handler address. This forces the instruction cache to fetch instructions corresponding to this
cache line from memory. The reset handler address must be aligned to the size of the instruction cache
line.
It is the responsibility of the first eight instructions of the reset handler to initialize the remainder of the
instruction cache. The Nios II initi instruction initializes a single instruction cache line. Do not use the
flushi instruction because it might cause undesired effects when used to initialize the instruction cache
in future Nios II implementations.
9-2
Defining Cache Properties
NII5V2
2015.05.14
Altera Corporation
Cache and Tightly-Coupled Memory
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