Specifications

Cache and Tightly-Coupled Memory
9
2015.05.14
NII5V2
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Nios II embedded processor cores can contain instruction and data caches. This chapter discusses cache-
related issues that you need to consider to guarantee that your program executes correctly on the Nios II
processor. Fortunately, most software based on the Nios II hardware abstraction layer (HAL) works
correctly without any special accommodations for caches. However, some software must manage the
cache directly.
For code that needs direct control over the cache, the Nios II architecture provides facilities to perform
the following actions:
• Initialize lines in the instruction and data caches
• Flush lines in the instruction and data caches
• Bypass the data cache during load and store instructions
This chapter discusses the following common cases in which you must manage the cache:
• Initializing cache after reset
• Writing device drivers
• Writing program loaders
• Managing cache in multi-master or multi-processor systems
This chapter covers cache management issues that affect Nios II programmers. It does not discuss the
fundamental operation of caches. Refer to The Cache Memory Book by Jim Handy for a discussion of
general cache management issues.
Nios II Cache Implementation
Depending on the Nios II core implementation, a Nios II processor system might or might not have data
or instruction caches. You can write programs generically so that they function correctly on any Nios II
processor, regardless of whether it has cache memory. For a Nios II core without one or both caches,
cache management operations are benign and have no effect.
The current Nios II cores have no hardware cache coherency mechanism. Therefore, if multiple masters
can access shared memory, software must explicitly maintain coherency across all masters.
For more information about the features of each Nios II core implementation, refer to the "Nios II Core
Implementation Details" chapter of the Nios II Processor Reference Handbook.
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