Specifications

Interrupt Funnels for External Interrupt Controllers
With the EIC interface, the Nios II processor supports a potentially unlimited number of hardware
interrupts on daisychained EICs. The interrupt priority level can be software-configurable. Details of
setting interrupt priorities depend on the particular EIC implementation. The hardware ensures that the
highest-priority interrupt is always serviced first.
You register ISRs at system initialization time. Interrupt dispatch is handled by hardware.
For more information, refer to the “Exception Handling System Structure” chapter.
Related Information
Exception Handling System Structure on page 8-25
Interrupt Funnels for Internal Interrupt Controllers
HAL Hardware Interrupt Funnel for the Internal Interrupt Controller
i = O
IRQ active?
NoYes
No
Exit
i = i + 1
i = = 32?
Enter
Call ISR
i
i
Yes
The HAL provides the following interrupt funnels:
• Shadow register set, pre-emption disabled
• Shadow register set, pre-emption enabled
• Nonmaskable interrupt
For more information, refer to the “Using Interrupt Funnels” chapter.
Related Information
Using Interrupt Funnels on page 8-11
Software Exception Funnel
Software exceptions can include unimplemented instructions, traps, and miscellaneous exceptions.
8-28
Interrupt Funnels for External Interrupt Controllers
NII5V2
2015.05.14
Altera Corporation
Exception Handling
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