Specifications

Figure 8-1: HAL Exception Handling System with the Internal Interrupt Controller
Hardware
interrupts
enabled?
Hardware
interrupts
pending?
Handle
software exception
No
Exit
Enter
NoYes
Yes
Restore context
Save context
Handle
hardware interrupts
31
ISR
ISR
1 0
ISR
Note: This figure shows the algorithm that the HAL general exception funnel uses to distinguish between
hardware interrupts and software exceptions.
Interrupt Funnel for the Internal Interrupt Controller
With the IIC, the Nios II processor supports 32 hardware interrupts. In the HAL funnel, hardware
interrupt 0 has the highest priority, and 31 the lowest. This prioritization is a feature of the HAL funnel,
and is not inherent in the Nios II interrupt controller.
The hardware interrupt funnel calls the user-registered ISRs. It goes through the IRQs in ipending
starting at 0, and finds the first (highest priority) active IRQ. Then it calls the corresponding registered
ISR. After this ISR executes, the funnel begins scanning the IRQs again, starting at IRQ
0
. In this way,
higher-priority interrupts are always processed before lower-priority interrupts. When all IRQs are clear,
the hardware interrupt funnel returns to the top level.
When the interrupt vector custom instruction is present in the Nios II processor, the HAL source detects
it at compile time and generates code using the custom instruction.
For more information, refer to the “Using the Interrupt Vector Custom Instruction” chapter.
Related Information
Using the Interrupt Vector Custom Instruction on page 8-23
NII5V2
2015.05.14
Interrupt Funnel for the Internal Interrupt Controller
8-27
Exception Handling
Altera Corporation
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