Specifications

generally invalid by the time you return the processor to normal execution. You must reset the processor
to return the system to a valid state.
With the IIC, the ipending register (ctl4) is masked to all zeros during single-stepping. This masking
prevents the processor from servicing interrupts that are asserted while you single-step through code. As a
result, if you try to single-step through a part of the exception handling system that reads the ipending
register, such as alt_irq_entry() or alt_irq_handler(), the code does not detect any pending
interrupts. This issue does not affect debugging software exceptions. You can set breakpoints in your ISR
code (and single-step through it), because the interrupt funnel has already used ipending to determine
which device caused the hardware interrupt.
HAL Exception Handling System Implementation
Theexception handling system implementation is one of many possible implementations of an exception
handling system for the Nios II processor. Some features of the HAL exception handling system are
constrained by the Nios II hardware, while others provide generally useful services.
You can take advantage of the HAL exception handling system without a complete understanding of the
HAL implementation.
For more information about how to install ISRs using the HAL API, refer to the “Nios II Interrupt Service
Routines” chapter.
Related Information
Nios II Interrupt Service Routines on page 8-6
Exception Handling System Structure
The exception handling system consists of the following components:
• The general exception funnel
• The software exception funnel
• The hardware interrupt funnel(s)
• An ISR for each peripheral that generates hardware interrupts
With the IIC, there is a single hardware interrupt funnel. This funnel manages processor context switch
and RTOS overhead (if any). It determines the source of the IRQ, and dispatches the correct ISR.
With an EIC, hardware interrupt funnels are configured by the EIC driver. With a vectored EIC, such as
the Altera VIC, there are multiple hardware interrupt funnels. Each funnel manages processor context
switch if necessary, and RTOS overhead if any. ISR dispatch is managed by hardware.
With the IIC, when the Nios II processor generates an exception, the general exception funnel receives
control. The general exception funnel passes control to either the hardware interrupt funnel or the
software exception funnel. The hardware interrupt funnel passes control to one or more ISRs.
Each time an exception occurs, the exception handling system services either a software exception or
hardware interrupts, with hardware interrupts having a higher priority. The HAL IIC support does not
include nested exceptions, but can handle multiple hardware interrupts per context switch.
For more information, refer to the “Hardware Interrupt Funnel” chapter.
NII5V2
2015.05.14
HAL Exception Handling System Implementation
8-25
Exception Handling
Altera Corporation
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