Specifications

Add a DMA Controller
A DMA controller performs bulk data transfers, reading data from a source address range and writing the
data to a different address range. Add DMA controllers to move large data buffers. This allows the Nios II
processor to carry out other tasks while data buffers are being transferred.
For more information about DMA controllers, refer to the "DMA Controller Core" and "Scatter-Gather
DMA Controller Core" chapters in the Embedded Peripherals IP User Guide.
Related Information
Embedded Peripheral IP User Guide
Place the Handler in Fast Memory
For the fastest execution of exception handler code, place the handler in a fast memory device. For
example, an on-chip RAM with zero wait states is preferable to a slow SDRAM. For best performance,
store exception handling code and data in tightly-coupled memory.
Use a Fast Nios II Core
For processing in both the exception context and the application context, the Nios II/f core is the fastest,
and the Nios II/e core (designed for small size) is the slowest.
Select Hardware Interrupt Priorities
Hardware interrupt priority levels can have a significant impact on system performance. If two interrupts
can be asserted at the same time, it is important to assign a higher priority level to the more critical
interrupt, so that it runs in preference to the less critical interrupt.
Hardware Interrupt Priorities with the Internal Interrupt Controller
When selecting the IRQ for each peripheral, remember that the HAL hardware interrupt funnel treats
IRQ
0
as the highest priority. Assign each peripheral’s interrupt priority based on its need for fast servicing
in the overall system. Avoid assigning multiple peripherals to the same IRQ.
Hardware Interrupt Priorities with an External Interrupt Controller
With an EIC, the hardware interrupt priority level can be more flexible than with the IIC. The method of
assigning priority levels to IRQs depends on the specific EIC implementation.
For example, with the Altera VIC, you can adjust hardware interrupt priority levels at runtime, with the
alt_vic_irq_set_level() function.
For more information about the VIC, refer to the "Vectored Interrupt Controller Core" chapter in the
Embedded Peripherals IP User Guide.
Related Information
Vectored Interrupt Controller Core
Debugging Nios II ISRs
You can debug an ISR by setting breakpoints in the ISR. The debugger completely halts the processor on
reaching a breakpoint. In the meantime, however, the other hardware in your system continues to
operate. Therefore, it is inevitable that other interrupts are ignored while the processor is halted. You can
use the debugger to step through the ISR code, but the status of other interrupt-driven device drivers is
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Add a DMA Controller
NII5V2
2015.05.14
Altera Corporation
Exception Handling
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