Specifications

Use Vectored Hardware Interrupts
By default, the Nios II processor has a nonvectored IIC. The HAL provides software to dispatch each
hardware interrupt to its specific ISR. By contrast, vectoring allows the processor to transfer control
directly to the ISR with minimal software intervention.
The options available for hardware interrupt vectoring depend on the interrupt controller configured in
the Nios II hardware, as described in this section.
Using the Interrupt Vector Custom Instruction
The Nios II processor core offers an interrupt vector custom instruction that accelerates hardware
interrupt vector dispatch in the HAL. You can include this custom instruction to improve your program’s
interrupt response time.
When the interrupt vector custom instruction is present in the Nios II processor, the HAL source detects
it at compile time and generates code using the custom instruction.
When using an interrupt vector custom instruction, you cannot use a separate exception stack.
Note:
The interrupt vector custom instruction is only available in hardware systems generated by SOPC
Builder.
For more information about the interrupt vector custom instruction, refer to “Interrupt Vector Custom
Instruction” in the "Instantiating the Nios II Processor" chapter of the Nios II Processor Reference
Handbook.
Related Information
• Using Tightly Coupled Memory with the Nios II Processor Tutorial
• Instantiating the Nios II Processor
Using an External Interrupt Controller
The Nios II EIC port allows you to connect a customizable external interrupt controller component. An
EIC can be vectored. An example is the Altera VIC.
For more information about the VIC, refer to the "Vectored Interrupt Controller Core" chapter in the
Embedded Peripherals IP User Guide.
Related Information
Vectored Interrupt Controller Core
Add Fast Memory
Increase the amount of fast on-chip memory available for data buffers. Ideally, implement tightly-coupled
memory that the software can use for buffers.
For more information about tightly-coupled memory, refer to the "Cache and Tightly-Coupled Memory"
chapter.
For more information about tightly-coupled memory, refer to the" Using Tightly Coupled Memory with
the Nios II Processor Tutorial.
Related Information
• Cache and Tightly-Coupled Memory
• Using Tightly Coupled Memory with the Nios II Processor Tutorial
• Instantiating the Nios II Processor
NII5V2
2015.05.14
Use Vectored Hardware Interrupts
8-23
Exception Handling
Altera Corporation
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