Specifications

Implement Time-Intensive Algorithms in Hardware
Processor-intensive tasks must often transfer large amounts of data to and from peripherals. A general-
purpose processor such as the Nios II processor is not the most efficient way to do this. Use direct
memory access (DMA) hardware if it is available.
For more information about programming with DMA hardware, refer to “Using DMA Devices” in the
"Developing Programs Using the Hardware Abstraction Layer chapter".
Related Information
Developing Programs Using the Hardware Abstraction Layer on page 6-1
Increase Buffer Size
If you are using DMA to transfer large data buffers, the buffer size can affect performance. Small buffers
imply frequent interrupts, which lead to high overhead.
Increase the size of the transaction data buffer(s).
Use Double Buffering
Using DMA to transfer large data buffers might not provide a large performance increase if the Nios II
processor must wait for DMA transactions to complete before it can perform the next task.
Double buffering allows the Nios II processor to process one data buffer while the hardware is transfer‐
ring data to or from another.
Keep Interrupts Enabled
When interrupts are disabled, the Nios II processor cannot respond quickly to hardware interrupt events.
Buffers and queues can fill or overflow. Even in the absence of overflow, maximum interrupt processing
time can increase after interrupts are re-enabled, because the ISRs must process data backlogs.
Disable interrupts as infrequently as possible, and for the briefest time possible.
Instead of disabling all interrupts, call alt_ic_irq_disable() and alt_ic_irq_enable() to enable and
disable individual interrupts.
To protect shared data structures, use RTOS structures such as semaphores.
Disable all interrupts only during critical system operations. In the code where interrupts are disabled,
perform only the bare minimum of critical operations, and reenable interrupts immediately.
Use Fast Memory
ISR performance depends on memory speed.
For best performance, place the ISRs and the stack in the fastest available memory: preferably tightly-
coupled memory (if available), or on-chip memory.
If it is not possible to place the main stack in fast memory, consider using a separate exception stack,
mapped to a fast memory section, as described in the next section.
For more information about mapping memory, refer to “Memory Usage” in the "Developing Programs
Using the Hardware Abstraction Layer" chapter.
For more information about tightly-coupled memory, refer to the "Cache and Tightly-Coupled Memory"
chapter.
Related Information
• Developing Programs Using the Hardware Abstraction Layer on page 6-1
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Implement Time-Intensive Algorithms in Hardware
NII5V2
2015.05.14
Altera Corporation
Exception Handling
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