Specifications

Table 8-2: HAL Interrupt Legacy and Enhanced API Functions to
Legacy API Function Enhanced API Function
alt_irq_register() alt_ic_isr_register()
alt_irq_disable() alt_ic_irq_disable()
alt_irq_enable() alt_ic_irq_enable()
If your upgraded driver might need to function in a BSP with legacy drivers, code it to support both APIs.
For more information, refer to the “Supporting Multiple Interrupt APIs” chapter.
Related Information
• Supporting Multiple Interrupt APIs on page 8-10
• HAL API Reference on page 14-1
Improving Nios II ISR Performance
If your software uses hardware interrupts extensively, the performance of ISRs is probably the most
critical determinant of your overall software performance.
Software Performance Improvements
In improving your ISR performance, you probably consider software changes first. However, in some
cases it might require less effort to implement hardware design changes that increase system efficiency.
For more information about hardware optimizations, refer to the “Hardware Performance Improve‐
ments” chapter.
The following sections describe changes you can make in the software design to improve ISR perform‐
ance.
Related Information
Hardware Performance Improvements on page 8-22
Execute Time-Intensive Algorithms in the Application Context
ISRs provide rapid, low latency response to changes in the state of hardware. They do the minimum
necessary work to clear the hardware interrupt condition and then return. If your ISR performs lengthy,
noncritical processing, it can interfere with more critical tasks in the system.
If your ISR requires lengthy processing, design your software to perform this processing outside of the
exception context. The ISR can use a message-passing mechanism to notify the application code to
perform the lengthy processing tasks.
Deferring a task is simple in systems based on an RTOS such as MicroC/OS-II. In this case, you can create
a thread to handle the processor-intensive operation, and the ISR can communicate with this thread using
any of the RTOS communication mechanisms, such as event flags or message queues.
You can emulate this approach in a single-threaded HAL-based system. The main program polls a global
variable managed by the ISR to determine whether it needs to perform the processor-intensive operation.
NII5V2
2015.05.14
Improving Nios II ISR Performance
8-17
Exception Handling
Altera Corporation
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