Specifications

HAL ISR Restrictions
When your system has an EIC, the HAL interrupt support imposes the following restrictions:
• Nonmaskable hardware interrupts must use a shadow register set.
• Nonmaskable hardware interrupts cannot share a register set with a maskable hardware interrupt.
Writing an ISR
The ISR you write must match the prototype that alt_ic_isr_register() expects. The prototype for
your ISR function must match the following prototype:
void (*alt_isr_func) (void* isr_context)
The parameter definition of context is the same as for the alt_ic_isr_register() function.
From the point of view of the HAL exception handling system, the most important function of an ISR is
to clear the associated peripheral’s interrupt condition. The procedure for clearing an hardware interrupt
condition is specific to the peripheral.
For more information, refer to the relevant chapter in the "Embedded Peripherals IP User Guide".
When the ISR has finished servicing the hardware interrupt, it must return to the HAL interrupt funnel
that called it.
Note: If you write your ISR in assembly language, use ret to return. The HAL interrupt funnel issues an
eret after restoring the application context.
Related Information
Embedded Peripheral IP User Guide
Using Interrupt Funnels
The HAL creates a vector table for each EIC connected to the Nios II processor. In the vector table, the
HAL inserts a branch to the correct funnel for each interrupt-driven device supported by the BSP,
depending on the device driver characteristics and pre-emption settings. Funnels can be shared by
multiple hardware interrupts, if the drivers have compatible characteristics.
The funnel code receives control from the general exception or interrupt vector, depending on which
interrupt controller is implemented. The funnel performs tasks such as switching the stack pointer, saving
registers and calling RTOS context-switch routines, and transfers control to the handler. When the
handler returns, the funnel code performs tasks such as calling RTOS process-dispatch routines and
restoring registers, and transfers control to the appropriate foreground task.
The HAL includes the following interrupt funnels:
• Shadow register set, pre-emption disabled—Hardware interrupt assigned to a shadow register set, with
pre-emption within the register set disabled. This funnel does not preserve register context. Hardware
guarantees that only one ISR runs with the shadow register set at any time.
• Shadow register set, pre-emption enabled—Hardware interrupt assigned to a shadow register set. An
interrupt can pre-empt another interrupt using the same register set. This funnel preserves register
context, so that handlers is assigned to the same register set do not corrupt one another’s context.
• Nonmaskable interrupt—Nonmaskable hardware interrupt assigned to a shadow register set, with pre-
emption within the register set disabled. This funnel does not preserve register context. Hardware
guarantees that only one ISR runs in the shadow register set at any time.
NII5V2
2015.05.14
HAL ISR Restrictions
8-11
Exception Handling
Altera Corporation
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