Specifications

The SBT inserts the following symbol definitions in system.h, indicating the configuration of the
processor’s interrupt-related hardware options:
• NIOS2_EIC_PRESENT—If defined, indicates that one or more EICs are present
• NIOS2_NUM_OF_SHADOW_REG_SETS—Indicates how many shadow register sets are present. The
maximum value is 63. If there are no shadow register sets, the value is 0.
The External Interrupt Controller Driver
To be compliant with the HAL enhanced interrupt API, the driver for an EIC must support the functions
listed under “The Enhanced HAL Interrupt API” chapter.
For more information, refer to the “The Enhanced HAL Interrupt API” chapter.
In addition, it can provide functions to support any special hardware features.
For more information, refer to the “Using the HAL Interrupt API with the VIC” chapter.
Related Information
• The Enhanced HAL Interrupt API on page 8-8
• Using the HAL Interrupt API with the VIC on page 8-9
Using the HAL Interrupt API with the VIC
The Altera driver for the VIC component supports the HAL enhanced interrupt API.
The VIC driver provides support for multiple, daisychained VIC devices. It also includes support for
shadow register sets. A BSP driver setting allows you to enable automatic pre-emption (fast nested
interrupts). Automatic pre-emption means that the Nios II processor leaves maskable exceptions enabled
when accepting a hardware interrupt.
For more information about fast nested interrupts, refer to “Exception Processing” in the "Programming
Model" chapter of the Nios II Processor Reference Handbook.
The VIC device driver also provides the following device-specific functions:
• int alt_vic_sw_interrupt_set(alt_u32 ic_id, alt_u32 irq);
• int alt_vic_sw_interrupt_clear(alt_u32 ic_id, alt_u32 irq);
• alt_u32 alt_vic_sw_interrupt_status(alt_u32 ic_id, alt_u32 irq);
• int alt_vic_irq_set_level(alt_u32 ic_id, alt_u32 irq, alt_u32 level);
For more information, refer to a detailed discussion of the VIC device-specific driver routinesin the
"Vectored Interrupt Controller Core" chapter in the Embedded Peripherals IP User Guide.
The EIC driver controls where hardware interrupt vector tables are located. For example, the Altera VIC
driver locates the vector table in the .text section by default, but allows you to position the vector table in
a different section with a driver setting.
Note:
The memory in which you place the vector table must be connected to both instruction and data
master ports on the Nios II processor.
Related Information
• Programming Model
• Vectored Interrupt Controller Core
The Legacy HAL Interrupt API
The legacy HAL interrupt API defines the following functions to manage hardware interrupt processing:
NII5V2
2015.05.14
The External Interrupt Controller Driver
8-9
Exception Handling
Altera Corporation
Send Feedback