Specifications

The processor’s response to hardware interrupts depends on which interrupt controller is implemented.
The following sections describe the hardware behavior with each interrupt controller.
For more information about the Nios II processor exception controller and hardware interrupt control‐
lers, including a list of optional exception types, refer to the "Processor Architecture" chapter of the Nios II
Processor Reference Handbook.
Related Information
• Invalid Instructions on page 8-32
• Processor Architecture
How the Internal Interrupt Controller Works
With the IIC, 32 independent hardware interrupt signals are available. These interrupt signals allow
software to prioritize interrupts, although the interrupt signals themselves have no inherent priority.
Note: With the IIC, Nios II exceptions are not vectored. Therefore, the same exception address receives
control for all types of exceptions. The general exception funnel at that address must determine the
type of software exception or hardware interrupt.
How an External Interrupt Controller Works
With an EIC, the Nios II processor supports an arbitrary number of independent hardware interrupt
signals. Interrupts are typically vectored, with interrupt priority levels associated in hardware. Vectoring
allows the Nios II processor to transfer control directly to each ISR. Hardware interrupt levels allow the
most critical interrupts to pre-empt lower-priority interrupts. Because both of these features are
implemented in hardware, the system can handle an interrupt without executing general exception funnel
code.
Note:
The details of hardware interrupt vectoring and prioritization are specific to the EIC implementa‐
tion.
For more information, refer to an example of an EIC implementation in the "Vectored Interrupt
Controller Core" chapter in the Embedded Peripherals IP User Guide.
Note:
The HAL supports external interrupt controllers only if they are connected in one of the following
ways:
• Directly to the Nios II EIC interface
• Through the daisy-chain port on another EIC
Related Information
Vectored Interrupt Controller Core
Nios II Interrupt Service Routines
Software often communicates with peripheral devices using hardware interrupts. When a peripheral
asserts its IRQ, it diverts the processor’s normal execution flow. When such an interrupt occurs, an
appropriate ISR must handle this interrupt and return the processor to its pre-interrupt state on
completion.
8-6
How the Internal Interrupt Controller Works
NII5V2
2015.05.14
Altera Corporation
Exception Handling
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