Specifications

Latency and Response Time
Exception (interrupt) latency, as defined in the previous section, is the time required for the hardware to
respond to an exception. Response time, in contrast, is the time required to begin executing code specific
to the exception cause, such as a particular ISR. Response time includes latency plus the time required for
the HAL to carry out some or all of the following overhead tasks:
• Context save—Saving registers on the stack
• RTOS context switch—Calling context-switch function(s) if an RTOS is implemented
• Dispatch handler—Determining the cause of the exception, and transferring control to a specific
handler or ISR
If you are concerned with system performance, response time is the more important than latency, because
it reflects the time elapsed between the physical event and the system’s specific response to that event.
Internal or External Interrupt Controller
The Nios II IIC is nonvectored, requiring the processor to dispatch ISRs with a software routine. An EIC,
by contrast, can be vectored. With a vectored EIC, such as the Altera
®
VIC, ISR dispatch is managed by
hardware, eliminating the processing time required for ISR dispatch, and substantially reducing hardware
interrupt response time.
An EIC has no impact on software exception latency or response time.
Shadow Register Sets
In conjunction with an EIC, shadow register sets speed up hardware interrupt response by making it
unnecessary to save registers on the stack. This feature has no impact on interrupt latency, but
significantly reduces interrupt response time.
Shadow register sets have no impact on software exception response time.
How the Hardware Works
The Nios II processor can respond to exceptions including software exceptions and hardware interrupts.
When the Nios II processor responds to an exception, it performs the following tasks:
• Saves the status register in estatus. This means that if hardware interrupts are enabled, the PIE bit
of estatus is set.
• Disables hardware interrupts.
• Saves the next execution address in ea (r29).
• Transfers control to the appropriate exception address, as follows:
• Software exception or internal hardware interrupt—Nios II processor general exception address
• External hardware interrupt—Device-specific interrupt address
All Nios II exception types are precise. This means that after an exception is handled, the Nios II
processor can re-execute the instruction that caused the exception.
The Nios II processor always re-executes the instruction after the software exception handler or ISR has
completed, when the exception processing system returns to the application context.
Several exception types, such as the advanced exceptions, are optional in the Nios II processor core. The
presence of these exception types depends on how the hardware designer configures the Nios II core at
the time of hardware generation.
NII5V2
2015.05.14
Latency and Response Time
8-5
Exception Handling
Altera Corporation
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