Specifications

When an external hardware interrupt occurs, the Nios II processor transfers control to an individual
vector address, which can be unique for each interrupt. The HAL provides the following services:
• Registering ISRs
• Setting up the vector table
• Transferring control from the vector table to your ISR
An EIC can be used with shadow register sets. A shadow register set is a complete alternate set of Nios II
general-purpose registers, which can be used to maintain a separate runtime context for an ISR.
An EIC provides the following information about each hardware interrupt:
Related Information
Vectored Interrupt Controller Core
Requested Handler Address
The requested handler address (RHA) specifies the address of the funnel associated with the hardware
interrupt. The availability of an RHA for each interrupt allows the Nios II processor to jump directly to
the interrupt funnel specific to the interrupting device, reducing interrupt latency.
Requested Interrupt Level
The Nios II processor uses the requested interrupt level (RIL) to prioritize the hardware interrupt request
versus any interrupt it is currently processing. While handling an interrupt, the Nios II processor
normally only takes higher-level interrupts.
Requested Register Set
If shadow register sets are implemented on the Nios II core, an EIC specifies a requested register set (RRS)
when it asserts an interrupt request. When the Nios II processor takes the hardware interrupt, the
processor switches to the requested register set. When an interrupt has a dedicated register set, the ISR
avoids the overhead of saving registers for a context switch.
Multiple hardware interrupts can be configured to share a register set. However, at run time, the Nios II
processor does not allow pre-emption between interrupts assigned to the same register set unless this
feature is specifically enabled. In this case, the ISRs must be written so as to avoid register corruption.
For more information, refer to an example of a driver that manages pre-emption within a register set in
the "Vectored Interrupt Controller Core" chapter in the Embedded Peripherals IP User Guide.
Related Information
Vectored Interrupt Controller Core
Requested NMI Mode
If the interrupt is configured as a nonmaskable interrupt (NMI), the EIC asserts requested NMI (RNMI).
Any hardware interrupt can be nonmaskable, depending on the configuration of the EIC. An NMI
typically signals a critical system event requiring immediate handling, to ensure either system stability or
deterministic real-time performance.
Shadow Register Sets
Although shadow register sets can be implemented independently of the EIC interface, typically the two
features are used together. Combining shadow register sets with an appropriate EIC, you can minimize or
eliminate the context switch overhead for critical hardware interrupts.
8-4
Requested Handler Address
NII5V2
2015.05.14
Altera Corporation
Exception Handling
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