Specifications

• Software exception—An exception caused by a software condition; that is, any exception other than a
hardware interrupt. This includes unimplemented instructions and trap instructions.
• Unimplemented instruction—An implementation-dependent instruction that is not supported on the
particular Nios II core implementation that is in your system. For example, in the Nios II/e core, mul
and div are unimplemented.
• Worst-case exception (or interrupt) latency—The value of the exception (or interrupt) latency,
including the maximum disabled time or maximum masked time. Including the maximum disabled or
masked time accounts for the case when the exception (or interrupt) occurs at the beginning of the
masked or disabled time.
Related Information
Miscellaneous Exceptions on page 8-31
Interrupt Controllers
The configuration of Nios II exception processing depends on the type of hardware interrupt controller.
You select the hardware interrupt controller when you instantiate the Nios II processor in the system
integration tool, Qsys or SOPC Builder.
For more information and details about selecting a hardware interrupt controller, refer to the "Instanti‐
ating the Nios II Processor" chapter of the Nios II Processor Reference Handbook.
Related Information
Instantiating the Nios II Processor
For more information and details about selecting a hardware interrupt controller.
Internal Interrupt Concepts
With the IIC, Nios II exception handling is implemented in classic RISC fashion. All exception types,
including hardware interrupts, are dispatched through a single top-level exception funnel. This means
that all exceptions (hardware and software) are handled by code residing at a single location, the
exception address.
The IIC is a simple, nonvectored hardware interrupt controller. Upon receipt of an interrupt request, the
IIC transfers control to the general exception address. The hardware indicates which IRQ is currently
asserted, and allows software to mask individual interrupts.
With the IIC, the HAL interrupt funnel identifies the hardware interrupt cause in software, and
dispatches the registered ISR.
The IIC is available in all revisions of the Nios II processor.
External Interrupt Concepts
The EIC interface enables the Nios II processor to work with a separate external interrupt controller
component. An EIC can be a custom component that you provide. Altera provides an example of an EIC,
the vectored interrupt controller (VIC).
For more information about the VIC, refer to the "Vectored Interrupt Controller Core" chapter in the
Embedded Peripherals IP User Guide.
With an EIC, hardware interrupts are handled separately from software exceptions. Hardware interrupts
have separate vectors and funnels. Each interrupt can have its own handler, or handlers can be shared.
Software exception handling is the same as with the IIC.
The EIC interface provides extensive capabilities for customizing your interrupt hardware. You can
design, connect and configure an interrupt controller that is optimal for your application.
NII5V2
2015.05.14
Interrupt Controllers
8-3
Exception Handling
Altera Corporation
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