Specifications

In a memory device containing the reset or exception address, the linker creates a normal (nonreserved)
memory section above the .entry or .exceptions section. If there is a region of memory below the .entry
or .exceptions section, it is unavailable to the Nios II software.
Assigning Code and Data to Memory Partitions
This section describes how to control the placement of program code and data in specific memory
sections. In general, the Nios II development flow specifies a sensible default partitioning. However, you
might wish to change the partitioning in special situations.
For example, to enhance performance, it is a common technique to place performance-critical code and
data in RAM with fast access time. It is also common during the debug phase to reset (that is, boot) the
processor from a location in RAM, but then boot from flash memory in the released version of the
software. In these cases, you must specify manually which code belongs in which section.
Figure 6-3: HAL Link Map - Unavailable Memory Region Below the .exceptions Section
ext_flash
sdram
ext_ram
epcs_controller
HAL Memory
Sections
Physical
Memory
.entry
.ext_flash
(unused)
.exceptions
.text
.rodata
.rwdata
.bss
.sdram
.ext_ram
.epcs_controller
Simple Placement Options
The reset handler code is always placed at the base of the .reset partition. The general exception funnel
code is always the first code in the section that contains the exception address. By default, the remaining
code and data are divided into the following output sections:
NII5V2
2015.05.14
Assigning Code and Data to Memory Partitions
6-37
Developing Programs Using the Hardware Abstraction Layer
Altera Corporation
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