Specifications

• Character mode devices
• UART core
• JTAG UART core
• LCD 16207 display controller
• Flash memory devices
• Common flash interface compliant flash chips
• Altera’s erasable programmable configurable serial (EPCS) serial configuration device controller
• File subsystems
• Altera host based file system
• Altera read-only zip file system
• Timer devices
• Timer core
• DMA devices
• DMA controller core
• Scatter-gather DMA controller core
• Ethernet devices
• Triple Speed Ethernet MegaCore
®
function
• Standard Microchip Solutions (SMSC) LAN91C111 10/100 Non-PCI Ethernet Single Chip MAC +
PHY
The LAN91C111 and Triple Speed Ethernet components require the MicroC/OS-II runtime environment.
For more information, refer to the "Ethernet and the NicheStack TCP/IP Stack - Nios II Edition" chapter.
Note:
Third-party vendors offer additional peripherals not listed here.
Related Information
• Ethernet and the NicheStack TCP/IP Stack - Nios II Edition on page 11-1
• Altera Embedded Alliance
List of other peripherals available for the Nios II processor.
Provide Partial HAL Support
All peripherals (both from Altera and third party vendors) must provide a header file that defines the
peripheral’s low-level interface to hardware. Therefore, all peripherals support the HAL to some extent.
However, some peripherals might not provide device drivers. If drivers are not available, use only the
definitions provided in the header files to access the hardware. Do not use unnamed constants, such as
hard-coded addresses, to access a peripheral.
Inevitably, certain peripherals have hardware-specific features with usage requirements that do not map
well to a general-purpose API. The HAL handles hardware-specific requirements by providing the UNIX-
style ioctl() function. Because the hardware features depend on the peripheral, the ioctl() options are
documented in the description for each peripheral.
Some peripherals provide dedicated accessor functions that are not based on the HAL generic device
models. For example, Altera provides a general-purpose parallel I/O (PIO) core for use with the Nios II
processor system. The PIO peripheral does not fit in any class of generic device models provided by the
HAL, and so it provides a header file and a few dedicated accessor functions only.
For complete details regarding software support for a peripheral, refer to the peripheral’s description.
NII5V2
2015.05.14
Provide Partial HAL Support
5-5
Overview of the Hardware Abstraction Layer
Altera Corporation
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