Specifications

Altera Corporation 5–11
October 2007 Nios II Processor Reference Handbook
Nios II Core Implementation Details
Execution performance for all instructions is shown in Table 5–6.
Exception Handling
The Nios II/f core supports the following exception types:
■ Hardware interrupt
■ Software trap
■ Unimplemented instruction
Table 5–6. Instruction Execution Performance for Nios II/f Core
Instruction Cycles Penalties
Normal ALU instructions (e.g., add, cmplt)1
Combinatorial custom instructions 1
Multi-cycle custom instructions 1 Late result
Branch (correctly predicted, taken) 2
Branch (correctly predicted, not taken) 1
Branch (mis-predicted) 4 Pipeline flush
trap, break, eret, bret, flushp, wrctl, and unimplemented instructions
4 Pipeline flush
call, jmpi
2
jmp, ret, callr
3
rdctl
1 Late result
load (without Avalon-MM transfer)
1 Late result
load (with Avalon-MM transfer)
> 1 Late result
store, flushd (without Avalon-MM transfer)
1
store, flushd (with Avalon-MM transfer)
> 1
initd
1
flushi, initi
4
Multiply (1) Late result
Divide (1) Late result
Shift/rotate (with hardware multiply using embedded multipliers) 1 Late result
Shift/rotate (with hardware multiply using LE-based multipliers) 2 Late result
Shift/rotate (without hardware multiply present) 1 - 32 Late result
All other instructions 1
Note to Ta bl e 5 – 6 :
(1) Depends on the hardware multiply or divide option. See Table 5–3 on page 5 for details.