Specifications

5–10 Altera Corporation
Nios II Processor Reference Handbook October 2007
Nios II/f Core
Only the A-stage and D-stage are allowed to create stalls.
The A-stage stall occurs if any of the following conditions occurs:
■ An A-stage memory instruction is waiting for Avalon-MM data
master requests to complete. Typically this happens when a load or
store misses in the data cache, or a flushd instruction needs to write
back a dirty line.
■ An A-stage shift/rotate instruction is still performing its operation.
This only occurs with the multi-cycle shift circuitry (i.e., when the
hardware multiplier is not available).
■ An A-stage divide instruction is still performing its operation. This
only occurs when the optional divide circuitry is available.
■ An A-stage multi-cycle custom instruction is asserting its stall signal.
This only occurs if the design includes multi-cycle custom
instructions.
The D-stage stall occurs if the following condition occurs and no M-stage
pipeline flush is active:
An instruction is trying to use the result of a late result instruction too
early. The late result instructions are loads, shifts, rotates, rdctl,
multiplies (if hardware multiply is supported), divides (if hardware
divide is supported), and multi-cycle custom instructions (if present).
Branch Prediction
The Nios II/f core performs dynamic branch prediction to minimize the
cycle penalty associated with taken branches.
Instruction Performance
All instructions take one or more cycles to execute. Some instructions
have other penalties associated with their execution. Late result
instructions have two cycles placed between them and an instruction that
uses their result. Instructions that flush the pipeline cause up to three
instructions after them to be cancelled. This creates a three-cycle penalty
and an execution time of four cycles. Instructions that require
Avalon-MM transfers are stalled until any required Avalon-MM transfers
(up to one write and one read) are completed.