Specifications

Altera Corporation 5–9
October 2007 Nios II Processor Reference Handbook
Nios II Core Implementation Details
Accessing tightly-coupled memory bypasses cache memory. The
processor core functions as if cache were not present for the address span
of the tightly-coupled memory. Instructions for managing cache, such as
initd and flushd, do not affect the tightly-coupled memory, even if the
instruction specifies an address in tightly-coupled memory.
Execution Pipeline
This section provides an overview of the pipeline behavior for the benefit
of performance-critical applications. Designers can use this information
to minimize unnecessary processor stalling. Most application
programmers never need to analyze the performance of individual
instructions.
The Nios II/f core employs a 6-stage pipeline. The pipeline stages are
listed in Table 5–5.
Up to one instruction is dispatched and/or retired per cycle. Instructions
are dispatched and retired in-order. Dynamic branch prediction is
implemented using a 2-bit branch history table. The pipeline stalls for the
following conditions:
■ Multi-cycle instructions
■ Avalon-MM instruction master port read accesses
■ Avalon-MM data master port read/write accesses
■ Data dependencies on long latency instructions (e.g., load, multiply,
shift).
Pipeline Stalls
The pipeline is set up so that if a stage stalls, no new values enter that
stage or any earlier stages. No “catching up” of pipeline stages is allowed,
even if a pipeline stage is empty.
Table 5–5. Implementation Pipeline Stages for Nios II/f Core
Stage Letter Stage Name
FFetch
D Decode
EExecute
M Memory
A Align
W Writeback