Specifications

5–6 Altera Corporation
Nios II Processor Reference Handbook October 2007
Nios II/f Core
addi r1, r1, 100 ; r1 = r1 + 100 (Depends on result of mul)
Shift and Rotate Performance
The performance of shift operations depends on the hardware multiply
option. When a hardware multiplier is present, the ALU achieves shift
and rotate operations in one or two clock cycles. Otherwise, the ALU
includes dedicated shift circuitry that achieves one-bit-per-cycle shift and
rotate performance. Refer to Table 5–6 on page 5–11 for details.
Memory Access
The Nios II/f core provides optional instruction and data caches. The
cache size for each is user-definable, between 512 bytes and 64 KBytes.
The Nios II/f core supports the bit-31 cache bypass method for accessing
I/O on the data master port. Addresses are 31 bits wide to accommodate
the bit-31 cache bypass method.
Instruction and Data Master Ports
The instruction master port is a pipelined Avalon
®
-MM master port. If the
core includes data cache with a line size greater than four bytes, then the
data master port is a pipelined Avalon-MM master port. Otherwise, the
data master port is not pipelined.
The instruction and data master ports on the Nios II/f core are optional.
A master port can be excluded, as long as the core includes at least one
tightly-coupled memory to take the place of the missing master port.
1 Although the Nios II processor can operate entirely out of
tightly-coupled memory without the need for Avalon-MM
instruction or data masters, software debug is not possible when
either the Avalon-MM instruction or data master is omitted.
Support for pipelined Avalon-MM transfers minimizes the impact of
synchronous memory with pipeline latency. The pipelined instruction
and data master ports can issue successive read requests before prior
requests complete.
Instruction and Data Caches
This section first describes the similar characteristics of the instruction
and data cache memories, and then describes the differences.