Specifications

5–4 Altera Corporation
Nios II Processor Reference Handbook October 2007
Nios II/f Core
Overview
The Nios II/f core:
■ Has separate instruction and data caches
■ Can access up to 2 GBytes of external address space
■ Supports optional tightly-coupled memory for instructions and data
■ Employs a 6-stage pipeline to achieve maximum DMIPS/MHz
■ Performs dynamic branch prediction
■ Provides hardware multiply, divide, and shift options to improve
arithmetic performance
■ Supports the addition of custom instructions
■ Supports the JTAG debug module
■ Supports optional JTAG debug module enhancements, including
hardware breakpoints and real-time trace
The following sections discuss the noteworthy details of the Nios II/f
core implementation. This document does not discuss low-level design
issues or implementation details that do not affect Nios II hardware or
software designers.
Arithmetic Logic Unit
The Nios II/f core provides several arithmetic logic unit (ALU) options to
improve the performance of multiply, divide, and shift operations.
Multiply and Divide Performance
The Nios II/f core provides the following hardware multiplier options:
■ DSP Block — Includes DSP block multipliers available on the target
device. This option is available only on Altera FPGAs that have DSP
Blocks.
■ Embedded Multipliers — Includes dedicated embedded multipliers
available on the target device. This option is available only on Altera
FPGAs that have embedded multipliers.
■ Logic Elements— Includes hardware multipliers built from logic
element (LE) resources.
■ None — Does not include multiply hardware. In this case, multiply
operations are emulated in software.
The Nios II/f core also provides a hardware divide option that includes
LE-based divide circuitry in the ALU.
Including an ALU option improves the performance of one or more
arithmetic instructions.